VXI VT1422A, User Manual

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Programming the VT1422A for Data Acquisition and Control 149 Chapter 4
Updating the Status System and VXIbus Interrupts
The driver needs to update the status system’s information whenever the
status of the VT1422A changes. This update is always done when the status
system is accessed or when CALibrate, INITiate, or ABORt commands are
executed. Most of the bits in the OPER and QUES registers represent
conditions which can change while the VT1422A is measuring (initiated).
In many circumstances, it is sufficient to have the status system bits updated
the next time the status system is accessed or the INIT or ABORt commands
are given. When it is desired to have the status system bits updated closer in
time to when the condition changes on the VT1422A, the VT1422A
interrupts can be used.
The VT1422A can send VXI interrupts upon the following conditions:
•
Trigger too Fast condition is detected. Trigger comes prior to trigger
system being ready to receive trigger.
•
FIFO overflowed. In either FIFO mode, data was received after the
FIFO was full.
•
Overvoltage detection on input. If the input protection jumper has not
been cut, the input relays have all been opened and a *RST is required
to reset the VT1422A.
•
Scan complete. The VT1422A has finished a scan list.
•
SCP trigger. A trigger was received from an SCP.
•
FIFO half full. The FIFO contains at least 32768 values.
•
Measurement complete. The trigger system exited the "Wait-For-Arm."
This clears the Measuring bit in the OPER register.
•
Algorithm executes an "interrupt()" statement.
These VT1422A interrupts are not always enabled since, under some
circumstances, this could be detrimental to the users system operation.
For example, the Scan Complete, SCP triggers, FIFO half full, and
Measurement complete interrupts could come repetitively, at rates that would
cause the operating system to be swamped by processing interrupts. These
conditions are dependent upon the user’s overall system design, therefore the
driver allows the user to decide which, if any, interrupts will be enabled.
The way the user controls which interrupts will be enabled is via the *OPC,
STATUS:OPER/QUES:ENABLE, and STAT:PRESET commands.
Each of the interrupting conditions listed above, has a corresponding bit in
the QUES or OPER registers. If that bit is enabled via the STATus:OPER/
QUES:ENABle command to be a part of the group summary bit, it will also
enable the VT1422A interrupt for that condition. If that bit is not enabled,
the corresponding interrupt will be disabled.
Sending the STAT:PRESET will disable all the interrupts from the
VT1422A.
Sending the *OPC command will enable the measurement complete
interrupt. Once this interrupt is received and the OPC condition sent to the
status system, this interrupt will be disabled if it was not previously enabled
via the STATUS:OPER/QUES:ENABLE command.