500-004941-000
3-6
d
Ω
/dt without lag. The output data will always be fresh and available as long as the
maximum tracking rate of the converter is not exceeded.
The converter automatically zero-sets all of the internal op amps twice
per carrier cycle near the zero crossings of the reference. This contributes to the
converter’s superior dynamic performance.
3.4.2
Digital Interface
The digital interface circuitry has three main functions: to latch the output
bits so that stable data can be read out; to furnish parallel, three-state data formats;
and to act as a buffer between the internal CMOS logic and the external TTL logic.
3.4.3
Solid State Differential Input Option
This option provides signal and reference inputs that are true differential
inputs with high AC and DC common mode rejection. Input impedance is
maintained with power off. The maximum transient peak voltage should not exceed
100 volts.
3.4.4
Direct Input Option
The direct input option provides for 2 Vrms resolver inputs. A 2 V input
from a resolver means that the reference voltage can be less than that of an 11.8 V
resolver, thus lowering the cost and power of the reference oscillator. However,
operation at a lower level makes the input more noise sensitive.
3.4.5
Logic Input/Output
The digital angle output consists of 10, 12, 14, or 16 parallel data bits and
a CONVERTER BUSY (CB) signal. All logic outputs are short-circuit proof to
ground and +5 volts. The CB output is a positive, 0.4 to 0.7 µs pulse. Data
changes about 50 ns after the leading edge of the pulse because of an internal
delay. Data is valid 0.2 µs after the leading edge of CB, and the angle is
determined by the sum of the bits at logic "1". Digital outputs are three-state and
provide two bytes; bits 1 through 8 (MSB) are enabled by the signal EM and bits 9
through 16 (LSB) are enabled by the signal EL.
Whenever an input angle change occurs, the converter changes the
digital angle in 1 LSB steps and generates a converter busy pulse. Output data
change is initiated by the leading edge of the CB pulse, delayed by 50 ns nominal.
Valid data is available at the outputs 0.2 µs after the leading edge of CB.
As long as the converter maximum tracking rate is not exceeded, there
will be no lag in the converter output. If a step input occurs, as when power is
initially applied, the response will be critically damped. After initial slewing at the
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