VSC8211 Evaluation Board
User Guide
Revision 1.0
December 2013
Vitesse Proprietary
Page 7 of 13
2.1.4
GMII, RGMII, MII, TBI and RTBI MAC Interface
The parallel MAC interfaces are available through pin headers on J16 and J28.
2.1.5
Fiber Transceiver Interface (SFP Cage)
The Fiber transceiver differential pair used in the SGMII to SerDes PHY operating mode
is supported with the standard SFP cage (U5).
2.1.6
Switches
Switch SW1 allows the user to select the mode of the EECLK/PLLMODE pin. In the on
position a logic high voltage (pull-up resistor) configures the device for a 125MHz
reference clock while a logic low voltage (pull-down resistor) selects a 25MHz
reference clock option. This is a momentary ON switch which requires the user to hold
it in the on position for 3 seconds during board power up or device reset.
2.1.7
Taitien 25MHz Crystal
The evaluation board is shipped configured to use the VSC8211’s internal on-chip
oscillator. The jumper on J13 should be installed in the XTAL (left) position, and the
jumper on J8 should be installed in the PLL enable or VCC (right) position.
Note
Review the required action for SW1 mentioned above.
2.1.8
External RefClk Option
The user may choose to provide an external PHY REFCLK via the SMA connector
(J12). The user must configure the device by installing a jumper on J8 in the PLL
disable or ground (left) position and installing a jumper on J13 in the SMA (right)
position.
2.1.9
Silabs Microcontroller
A Silabs F340 microcontroller is included to facilitate a software interface to the
registers on the VSC8211
through a USB port.
To communicate to the EEPROM or to use a Rabbit microcontroller rather than the
Silabs F340, install jumpers on J23 and J14 accordingly.
Note
A silk-screen error exists on the PCB for J23 such that the MDIO and MDC
signals are swapped with the SDA and SCL signals respectively for the F340 and
Rabbit signals. Refer to Figure 2 for clarity of the default configuration.