1 March, 2005
V1629OM.DOC/ A
Page 4 of 10
2.2 INSERTION
DELAY
The SDI insertion delay is
10ns
.
The insertion delay from the SDI de-serialiser to the analogue outputs is
1.44
µ
s
. This is the same for
the both the YC and CVBS outputs.
2.3 HARDWARE
The figure below shows diagrammatically the main board along with certain components of interest. In
particular it shows the positions of the 8 way DIL switches and the programmable micro-controller
devices for each channel. The small PROM, U27, holds the data for the programmable FLEX device,
U20.
FRONT PANEL
REAR CONNECTOR
PROM
SW1
U27
FS1
1
8
U16
uP A
SW2
1
8
U28
uP B
VR1
VR2
VR3
VR4
VR5
VR6
on
off
off
on
2.4 ADJUSTMENTS
The drawing in section 2.3 shows 6 variable resistors pots. These are defined here.
POT PURPOSE
VR 1
CH A CVBS O/P Black Level
= 0V ±10mV (PAL I)
VR 2
CH A Y O/P Black Level
= 0V ±10mV (PAL I)
VR 3
CH A Overall O/P Level
= 700mV ±10mV (PAL I)
VR 4
CH B CVBS O/P Black Level
= 0V ±10mV (PAL I)
VR 5
CH B Y O/P Black Level
= 0V ±10mV (PAL I)
VR 6
CH B Overall O/P Level
= 700mV ±10mV (PAL I)
All levels are set up in the factory, and while the information is given here it is not expected that users
and operators will need to make any adjustments in the field over the expected lifetime of the
equipment.
