UG:305
Page 3
ADDR0
A
DDR
1
EA
IN
SYNC
O
SYNC
I
EA
O
+V
O
SENS
E
PG
D
Tie
VD
R
-VO SENSE
VD
R
SYNC
O
SYNC
I
PG
D
EN
AB
LE
COMP
TR
K
SC
L
SD
A
VS1
VS2
EA
O
TR
K
SGND
1
DN
P
SGND
2
DN
P
PG
SENS
E
VI
N_
F
LGH
A7
EN
A5
SY
NC
I
B1
VDIF
F
A1
1
VS1
K4
EA
IN
A1
2
VS
P
A1
0
VS
N
A9
COMP
A8
SY
NC
O
C1
SC
L
A3
AD
DR
0
A2
AD
DR
1
A1
SD
A
A4
TRK
A6
SGND
B14
EAO
A13
VD
R
E1
VS1
K5
VOUT
J1
4
VOUT
K1
3
VI
N
J1
PG
D
D1
VI
N
H1
PG
ND
K7
VI
N
K1
VS2
K10
VI
N
K2
VI
N
G1
VOUT
H1
4
VOUT
G1
4
PG
ND
K8
VOUT
K1
4
VS2
K11
IM
ON
A1
4
IS
+
E1
4
IS
-D1
4
PI374
1
CT
RK
CC
OM
P
CEAO
RP
GD
ADDRO/FT2
ADDR1/FT
1
CVDR
RSYNCI
C1
C2
C3
C4
C5
C7
C8
C9
C1
0
C1
1
C1
2
1
J2
1
J3
1
J1
1
J4
PG
ND
VI
N
VOUT
VI
N_
FILT
RSENSE
IMON
DN
P
R1
DN
P
R3
DN
P
R2
DN
P
R4
ADDR
1
AD
DR
0
VD
R
IMON
JV
IN
JV
OU
T
VS
P
VDIF
F
VS
N
VSP
C6
IS
N
C1
3
C1
4
DN
P
RIMO
N
RI
N
IS
P
Ti
e
VO
UT
VI
N
AD
DR
0
ADDR1
SY
NC
O
VD
R
DA
C
VI
N_FILT
IS
N
SD
A
SCL
ENABLE
EA
O
VS
P
VD
IF
F
PG
D
VS
N
SY
NC
I
1 2 3 4 5 6 7 8
P1
P2
P3
P4
SAMTEC LPHS-04-24
9 10 11 12
13 14 15 16 17 18 19 20 21 22 23 24
CN
1
SAMT
EC
LP
HS
HO
RZ
Edge
Conn
VS
N
VDIF
F
RD
IFF1
RD
IFF2
REA1
REA4
RG
P
JG
P
CEAIN1
DN
P
EX
T_
VREF
REA3
DN
P
REA2
DA
C
PCBNumbe
r
DN
P
RZ
2
RZ
1
VS
P
IMON
Ju
mp
er
J5 to
co
nn
ect
IM
ON to
VP
fo
r AT
E Te
s
ng
.
DN
P
CIN
2
J6
SG
ND
ENABLE
VSU
PP
LY
FP
04
04
R1
L1
CI
N1
Tie
A1
1
GND
2
A2
3
Y2
4
VCC
5
Y1
6
U1 N
C7W
Z14
2
3
D1
A
1
4
D1
B
R5
VD
R
4
1
2
3
TO
P VI
EW
DUAL
LE
D ORIENTATIO
N
PG
D
PCBNumbe
r
1
2
MECH
PI
N
3
HC
V1
20
6-
R
LMAG
F1
F2
Fiducia
ls
PCB020
3
-VO SENSE
1
+
VO
SENSE
1
SGND
1
EN
2
SD
A
3
SC
L
4
H1
Factory Test Header
J5
SG
ND
RS
CL
RSDA
Figure 1
Evaluation board schematic
