BIOS
Page 4-9
LDT & PCI Bus Control
Scroll to LDT & PCI Bus Control and press <Enter>. The following screen appears:
Upstream LDT Bus Width
Options: 8 bit, 16 bit.
Downstream LDT Bus Width
Options: 8 bit, 16 bit.
LDT Bus Frequency
This item sets CPU Hyper Transport front size bus.
Options: Auto, 800MHz, 600MHz, 400MHz, 200MHz.
PCI1/2 Master 0 WS Write
When Enabled, Writes to the PCI bus are commanded with zero wait states.
Options: Enabled, Disabled.
PCI1/2 Post Write
Enables CPU to PCI bus POST write.
Options: Enabled, Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.2.
Options: Enabled, Disabled.
