Analog Input
38
– Reference
VSBC-8 Reference Manual
ADC D
ATA
L
OW
R
EGISTER
ADCLO (READ) 00E4h (or 1E4h via CMOS Setup)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
The ADCLO register is a read register containing the lower 8 bits of data from the A/D
conversion results. It is used in conjunction with the ADCHI register to read the complete 12-bit
data word.
After a conversion is complete (as reported by the DONE bit in the ADCSTAT register) the
ADCLO register should be read first, followed by the ADCHI register. A word-wide input
instruction from the ADCLO register (in ax,dx) will fetch data from both registers in the proper
sequence.
The data registers are located on an even address boundary to facilitate efficient single-cycle
reading of the A/D data.
Table 20: ADCLO Bit Assignments
Bit
Mnemonic
Description
D7-D0
ADCDATA
A/D Input Data (Least Significant Byte)
— These bits contain data
bits D7 through D0 of the conversion results.
