VersaLogic VSBC-8, Reference Manual

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Analog Input
36 – Reference VSBC-8 Reference Manual
D
IGITAL
C
ONTROL
/ A
NALOG
S
TATUS
R
EGISTER
DCAS (READ/WRITE) 00E2h (or 1E2h via CMOS Setup)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved Reserved Reserved Reserved Reserved DONE DIRHI DIRLO
Table 18: Digital Control / Analog Status Register Bit Assignments
Bit Mnemonic Description
D7-D3 Reserved Reserved
—
These bits have no function.
D2 DONE
Analog Input Conversion Complete — This status bit is used to
determine when it is OK to read data from the A/D converter.
DONE = 0 Conversion underway, data not yet available.
DONE = 1 Analog input conversion has completed. Valid data is
available to be read from the ADCLO and ADCHI registers.
Done is reset to “0” when a new conversion is started.
Note! This bit is not valid until an A/D conversion cycle has been triggered.
D1 DIRHI Direction Control for Opto 22 Digital I/O Hi Port — This bit controls the
input/output direction of the digital I/O signals DIO8–DIO15.
DIRHI = 0 Input
DIRHI = 1 Output
Note! See page 42 for further information.
D0 DIRLO Direction Control for Opto 22 Digital I/O Lo Port — This bit controls the
input/output direction of the digital I/O signals DIO0–DIO7.
DIRLO = 0 Input
DIRLO = 1 Output
Note! See page 42 for further information.