VersaLogic Komodo VL-EPICs-36 Reference Manual Download | Manualshive

Page: 38 / 57

background image

Interfaces and Connectors

VL-EPICs-36 Reference Manual

32

Audio (J6)

The audio interface on the VL-EPICs-36 is implemented using the IDT 92HD75B Audio Codec.
This interface is compatible with Intel’s High Definition (HD) Audio Interface and is Microsoft
WLP 3/4 premium logo compliant, as defined in WLP 3.09. Drivers are available for most
Windows-based operating systems. To obtain the most current versions, consult the

36 product page

J6 provides the line-level stereo input and line-level stereo output connection points. The outputs
will drive any standard-powered PC speaker set.

These connectors use IEC 61000-4-2-rated TVS components to help protect against ESD
damage.

S

OFTWARE

C

ONFIGURATION

The audio interface uses PCI interrupt INTA#. CMOS Setup is used to select the IRQ line routed
to INTA#.

The audio controller can be disabled in CMOS Setup.

Table 11: Audio Connector Pinout

J6

Pin

Signal
Name

Function

1

AUDOUTR

Audio Line-Out Right

2

GND

Ground

3

AUDOUTL

Audio Line-Out Left

4

GND

Ground

5

AUDINR

Audio Line-In Right

6

GND

Ground

7

AUDINL

Audio Line-In Left

8

GND

Ground

«
...
36
37
38
39
40
...
»

Summary of Contents for Komodo VL-EPICs-36

Page 1: ...Reference Manual REV November 2020 VL EPICs 36 Komodo Intel Core 2 Duo Based SBC with Ethernet Video SUMIT and PC 104 interface ...

Page 2: ... makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose VersaLogic reserves the right to revise this product and associated documentation at any time without obligation to notify anyone of such changes PC 104 and the PC 104 logo are trademarks of the PC 104 Consortium The SUMIT n...

Page 3: ...e contains additional information and resources for this product including Reference Manual PDF format Operating system information and software drivers Data sheets and manufacturers links for chips used in this product BIOS information and upgrades This is a private page for VL EPICs 36 users that can be accessed only be entering this address directly It cannot be reached from the VersaLogic home...

Page 4: ...c Setup 8 Operating System Installation 10 Physical Details 11 Dimensions and Mounting 11 VL EPICs 36 Dimensions 11 VL CBR 5009 Dimensions 12 Hardware Assembly 13 Standoff Locations 13 External Connectors 14 VL EPICs 36 Connector Locations Top 14 VL EPICs 36 Connector Locations Bottom 15 VL EPICs 36 Connector Functions and Interface Cables 16 Connector Locations VL CBR 5009 17 VL CBR 5009 Connecto...

Page 5: ...le Redirection 28 PCI Express SUMIT Connectors J2 J3 29 Ethernet Interface J5 LED J4 31 BIOS Configuration 31 Ethernet Connector J5 31 Ethernet LED J4 31 Audio J6 32 Software Configuration 32 PC 104 ISA Expansion Bus J7 J8 33 PC 104 I O Support 33 PC 104 Memory Support 33 IRQ Support 33 DMA Support 33 SATA Interface J10 J15 34 USB Interface Multiple Connectors 34 BIOS Configuration 35 eUSB Interfa...

Page 6: ...ents VL EPICs 36 Reference Manual vi SPI Registers 43 Interrupt Configuration 46 Special Registers 48 Product Code Register 48 Revision Level Register 49 Special Control Register 50 Appendix A References 51 ...

Page 7: ... COM ports 460K baud max Expansion with VersaLogic SPX add on I O modules EPIC compliant 4 5 x 6 5 footprint Field upgradeable BIOS with OEM enhancements Customizing available The VL EPICs 36 is a SUMIT EPIC single board computer with an Intel Core 2 Duo processor The board is compatible with popular operating systems such as Windows QNX VxWorks and Linux The VL EPICs 36 features high reliability ...

Page 8: ...net Interface Intel 82574IT based 10BaseT 100GBaseTX 1000BaseT Ethernet Controller COM1 2 Interface RS 232 16C550 compatible 115 kbps max full 9 wire COM3 4 Interface RS 232 422 485 16C550 compatible 460 kbps max 4 wire RS 232 USB Ten USB 2 0 Four USB type A ports on board four channels on SUMIT A connector one channel on MiniBlade and one on eUSB Audio HD audio CODEC Stereo Line in and Stereo Lin...

Page 9: ...Introduction VL EPICs 36 Reference Manual 3 VL EPICs 36 Block Diagram Figure 1 System Block Diagram ...

Page 10: ... C the CPU will turn itself off to prevent damage to the chip Note Intel does not warrant their CPUs in the event of this occurrence MODEL DIFFERENCES VersaLogic offers both standard and extended temperature models of the VL EPM 35 The basic operating temperature specification for both models is shown below VL EPICs 36S 0 C to 60 C free air no airflow VL EPICs 36E 40 C to 85 C free air To reliably...

Page 11: ...components The circuit board must only be handled at an ESD workstation If an approved station is not available some measure of protection can be provided by wearing a grounded antistatic wrist strap Keep all plastic away from the board and do not slide the board over any surface After removing the board from its protective wrapper place the board on a grounded static free surface component side u...

Page 12: ...ineers are also available via e mail at Support VersaLogic com REPAIR SERVICE If your product requires service you must obtain a Returned Material Authorization RMA number by calling 503 747 2261 Please provide the following information Your name the name of your company and your phone number The name of a technician or engineer that can be contacted if any questions arise Quantity of items being ...

Page 13: ...Introduction VL EPICs 36 Reference Manual 7 Note Please mark the RMA number clearly on the outside of the box before returning ...

Page 14: ...steps outline the procedure for setting up a typical development system The VL EPICs 36 should be handled at an ESD workstation or while wearing a grounded antistatic wrist strap Before you begin unpack the VL EPICs 36 and accessories Verify that you received all the items you ordered Inspect the system visually for any damage that may have occurred in shipping Contact Support VersaLogic com immed...

Page 15: ...on the bottom of the board Attach the adapter cable to the LVDS display Plug a USB keyboard and USB mouse into any Type A USB connector on the board J11 J12 J16 or J17 Plug the SATA hard drive data cable VL CBR 0701 into a SATA socket J10 or J15 Attach a SATA hard drive to the cable J20 ATX Power Supply LVDS USB Keyboard and USB Mouse SATA Hard Drive USB CD ROM Drive OS Installation CD ROM VL EPIC...

Page 16: ... Select a Boot Drive During startup press the B key to display the boot menu Insert the OS installation CD in the CD ROM drive and select to boot from the CD ROM drive 7 Install Operating System Install the operating system according to the instructions provided by the OS manufacturer See Operating System Installation Note If you intend to operate the VL EPICs 36 under Windows XP or Windows XP Emb...

Page 17: ...omplies with all PC 104 Express standards Dimensions are given below to help with pre production planning and layout Figure 3 VL EPICs 36 Dimensions and Mounting Holes Not to scale All dimensions in inches 3 3 6 096 4 128 4 328 2 596 5 496 0 200 5 596 2 446 0 000 3 375 0 200 0 000 3 250 1 950 Heatsink fan mounting ...

Page 18: ...ysical Details VL EPICs 36 Reference Manual 12 VL CBR 5009 DIMENSIONS Figure 4 VL CBR 5009 Dimensions and Mounting Holes Not to scale All dimensions in inches 5 50 5 10 1 175 1 95 1 575 1 325 0 065 1 875 ...

Page 19: ...to secure all eight standoffs A and B to the mounting surface to prevent circuit board flexing Four standoffs B must be used under the stack These are secured with four male female standoffs C threaded from the top side which also serve as mounting struts for the SUMIT PC 104 stack Standoffs are secured to the top circuit board using pan head screws See page 11 for dimensional details Four standof...

Page 20: ...S TOP Figure 6 Connector Locations Top J1 VGA J2 SUMIT B PCIe J22 SPX J5 Ethernet J6 Audio J7 J8 PC 104 ISA J9 Fan J10 J15 J12 J17 J11 J16 J13 User I O J14 Power J3 SUMIT A PCIe Intel ICH9M Intel GM45 Intel Core 2 Duo J24 Factory J4 Ethernet LED J11 USB1 J16 USB0 J10 SATA1 J15 SATA0 J12 USB3 J17 USB2 ...

Page 21: ...Physical Details VL EPICs 36 Reference Manual 15 VL EPICS 36 CONNECTOR LOCATIONS BOTTOM Figure 7 Connector Locations Bottom J21 SO DIMM J19 MiniBlade J20 LVDS J23 eUSB ...

Page 22: ...00mm 19 75 7 pin straight to straight SATA data friction or mechanical latching ATX to SATA power adapter 3 968 4 265 34 J11 USB 1 Standard USB Type A 3 783 4 667 34 J12 USB 3 Standard USB Type A 3 783 5 387 34 J13 COM 1 4 PLED keyboard mouse reset speaker FCI 89361 750LF VL CBR 5009 18 2mm 50 pin to 50 pin IDC to breakout board VL CBR 5009B 1 916 6 140 36 J14 Main Power Input Molex 39 01 2100 Mol...

Page 23: ...eader J2 Soft Reset Button Input Conta Clip 10250 4 5 pin screw terminal J3 COM1 COM2 Kycon K42 E9P P A4N Dual stacked DB 9 male J4 PS 2 Keyboard and Mouse Kycon KMDG 6S 6S S4N Dual stacked PS 2 female J5 COM4 Conta Clip 10250 4 5 pin screw terminal J6 COM3 Conta Clip 10250 4 5 pin screw terminal S1 Reset Button E Switch 800SP9B7M6RE Right angle momentary switch SP1 Speaker Challenge Electronics D...

Page 24: ...Physical Details VL EPICs 36 Reference Manual 18 Jumper Blocks JUMPERS AS SHIPPED CONFIGURATION Figure 9 Jumper Block Locations V2 V1 V3 1 2 3 2 1 4 3 1 2 V2 V3 V1 ...

Page 25: ...upport asp for more information Out 23 V2 1 2 3 CMOS RAM and Real Time Clock Erase 1 2 In Normal 2 3 In Erase CMOS RAM and Real Time Clock V2 1 2 In 22 V3 1 2 COM3 Rx End point Termination In 120 Ohm termination active Out No termination Places terminating resistor across COM3 RS 485 TXRX TXRX or RS 422 RX RX differential pair In 37 V3 3 4 COM4 Rx End point Termination In 120 Ohm termination activ...

Page 26: ...wer Input 8 5VDC Power Input 9 12VDC Power Input 10 GND Ground Note The 3 3VDC 12VDC and 12VDC inputs are required only for expansion modules that require these voltages POWER REQUIREMENTS The VL EPICs 36 requires 5 volts 5 for proper operation The higher voltages required for the RS 232 ports are generated as needed on board Low voltage supply circuits provide the many power rails required by the...

Page 27: ...wire should not exceed 18 Avoid using any additional connectors in the power delivery system The power and ground leads should be twisted together or as close together as possible to reduce lead inductance A separate conductor must be used for each of the power pins All 5V pins and all ground pins must be independently connected between the power source and the power connector Implement the remote...

Page 28: ...MORY AND SOLID STATE DRIVE The VersaLogic VL MF7 Series modules provide 1 or 2 GB of RAM plus 8 GB of flash storage The solid state drive SSD can function as a bootable SATA drive or secondary storage device without claiming either of the SATA channels at connectors J10 or J15 CMOS RAM CLEARING CMOS RAM You can move the V2 jumper to position 2 3 for a minimum of three seconds to erase the contents...

Page 29: ...r has been removed from the board PRIMARY AND BACKUP BIOS The Primary system BIOS is field upgradeable using the BIOS upgrade utility see the VL Epics 36 Product Page for more information Jumper VN 1 2 controls whether the system uses the Primary or Backup BIOS By default the Primary BIOS is selected jumper removed Real Time Clock The VL EPICs 36 features a year 2000 compliant battery backed 14681...

Page 30: ...fine FANTACHREG 0x28 define RLSREG 0x40 define RTOFFSET 0X70 define START 0x01 void main int baseIOHigh int baseIOLow int FTraw int Bindex int Bdata double fanRPM char keypressed 0 _clearscreen _GCLEARSCREEN _settextposition 2 1 printf FANTACH DEMO press ESC to quit n Set SIO Hardware Monitor IRQ and read in the HWM base address outp SIOINDEX 0x55 Enter SIO config mode outp SIOINDEX 0x07 Point to ...

Page 31: ...tp Bindex FANTACHREG 1 Fantach 1 MSB FTraw inp Bdata 8 FTraw now contains the number of 90KHz pulses it took to find 5 tach edges 5 edges 2 tach pulses 1 revolution Convert Raw to RPMs RPM 1 FTraw 11 11uS 2 60 fanRPM FTraw 0 00001111 fanRPM 2 fanRPM 1 fanRPM _settextposition 4 1 if fanRPM 0 printf FanTach 1 5 0fRPMs n fanRPM 60 delay 100 else printf FanTach 1 Stalled n delay 100 exit 0 ...

Page 32: ...amount of RAM used for video is set with a CMOS Setup option The VL EPICs 36 supports two types of video output SVGA and LVDS flat panel display which can be output simultaneously SVGA OUTPUT CONNECTOR J1 Adapter cable VL CBR 1201 is available to translate the J1 connector into a standard 15 pin D Sub SVGA connector This connector uses IEC 61000 4 2 rated TVS components to help protect against ESD...

Page 33: ... these options do not match the requirements of the panel you are attempting to use contact Support VersaLogic com for a custom video BIOS The 3 3V power provided to pins 19 and 20 of J20 is protected by a 1 Amp fuse Table 6 LVDS Flat Panel Display Pinout J20 Pin Signal Name Function 1 GND Ground 2 NC Not Connected 3 LVDSA3 Diff Data 4 LVDSA3 Diff Data 3 5 GND Ground 6 LVDSCLK0 Differential Clock ...

Page 34: ... a serial communications port CMOS Setup and some operating systems such as DOS can use this console for user interaction Console redirection settings are configured on the Features tab of the CMOS Setup The default setting On Remote User Detect causes the console not be redirected to the serial port unless a signal a Ctrl C character is detected from the terminal Console redirection can also be s...

Page 35: ...to master 13 USB_OC 2 3 USB overcurrent flag 2 3 14 SPI uWire_CLK SPI clock 15 5V 5V power 16 SPI uWire_CS0 SPI chip select 0 17 USB3 USB3 data 18 SPI uWire_CS1 SPI chip select 1 19 USB3 USB3 data 20 Reserved Do not use 21 5V 5V power 22 LPC_DRQ LPC DMA request 23 USB2 USB2 data 24 LPC_AD0 LPC line 0 25 USB2 USB2 data 26 LPC_AD1 LPC line 1 27 5V 5V power 28 LPC_AD2 LPC line 2 29 USB1 USB1 data 30 ...

Page 36: ...round 20 GND Ground 21 C_PETp1 PCIe link C lane 1 transmit 22 C_PRTp1 PCIe link C lane 1 transmit 23 C_PETn1 PCIe link C lane 1 transmit 24 C_PERn1 PCIe link C lane 1 transmit 25 GND Ground 26 GND Ground 27 C_PETp2 PCIe link C lane 2 transmit 28 C_PERp2 PCIe link C lane 2 transmit 29 C_PETn2 PCIe link C lane 2 transmit 30 C_PERn2 PCIe link C lane 2 transmit 31 GND Ground 32 GND Ground 33 C_PETp3 P...

Page 37: ...d to each PCI interrupt line ETHERNET CONNECTOR J5 A board mounted RJ 45 connector is provided to make connection with a Category 5 or 6 Ethernet cable The 82574IT Ethernet controller auto negotiates connection speed The interface uses IEC 61000 4 2 rated TVS components to help protect against ESD damage ETHERNET LED J4 Connector J4 provides an on board Ethernet LED interface The 3 3V power suppli...

Page 38: ...J6 provides the line level stereo input and line level stereo output connection points The outputs will drive any standard powered PC speaker set These connectors use IEC 61000 4 2 rated TVS components to help protect against ESD damage SOFTWARE CONFIGURATION The audio interface uses PCI interrupt INTA CMOS Setup is used to select the IRQ line routed to INTA The audio controller can be disabled in...

Page 39: ...h 07Fh 0A2h 0A3h 0A6h 0A7h 0AAh 0ABh 0AEh 0AFh 0B6h 0B7h 0BAh 0BBh 0BEh 0BFh 0D2h 0DDh 0E0h 0EFh 0F1h 207h 210h 3BFh 3E0h 4CFh 4D2h 4FFh 580h BFFh D00h Available base I O addresses for COM ports are 220h 228h 238h 338h 3F8h 2F8h 3E8h and 2E8h PC 104 MEMORY SUPPORT Memory ranges supported A0000h B7FFFh D0000h DFFFFh IRQ SUPPORT The following IRQs are available on the PC 104 bus IRQ 3 IRQ 4 IRQ5 and...

Page 40: ...nnectors If the power supply you are using does not provide SATA connectors adapters are available Table 12 SATA Port Pinout J10 or J15 Pin Signal Name Function 1 GND Ground 2 TX Transmit 3 TX Transmit 4 GND Ground 5 RX Receive 6 RX Receive 7 GND Ground USB Interface Multiple Connectors The VL EPICs 36 includes ten USB ports as shown below Table 13 USB Port Locations Port Connector Type USB0 J16 U...

Page 41: ...ERFACE J23 The VL EPICs 36 includes one eUSB port as shown below The VersaLogic VL F15 Series of eUSB SSD modules are available in sizes of 2 MB or 4 MB Contact VersaLogic Sales to order Table 14 eUSB Port Locations J23 Pin Signal Name Function 1 5V Protected Power Supply 2 NC Not connected 3 D Data 4 NC Not connected 5 D Data 6 NC Not connected 7 GND Ground 8 NC Not connected 9 Key Physical key 1...

Page 42: ... Ground Ground 6 8 Clear to Send 30 2 RXD RxD 7 4 Data Terminal Ready 31 3 CTS RxD 8 9 Ring Indicator 32 Ground Ground 9 5 Ground 33 Mouse 4 5 0V Protected 10 COM2 10 Data Carrier Detect 34 J4 1 Mouse Data 11 J3 15 Data Set Ready 35 Top 3 Ground 12 Bottom DB9 11 Receive Data 36 5 Mouse Clock 13 16 Request to Send 37 PBRESET 1 Pushbutton Reset 14 12 Transmit Data 38 S1 2 Ground 15 17 Clear to Send ...

Page 43: ...r COM4 The termination resistor should be enabled for RS 422 and the RS 485 endpoint station It should be disabled for RS 232 and the RS 485 intermediate station If RS 485 mode is used the differential twisted pair TxD RxD and TxD RxD is formed by connecting both transmit and receive pairs together For example on VL CBR 5009 connectors J6 and J5 the TxD RxD signal is formed by connecting pins 3 an...

Page 44: ...4 2 rated TVS components to help protect against ESD damage Table 16 COM1 2 Pinout VL CBR 5009 Connector J3 COM1 COM2 Top DB9 J3 Pin Bottom DB9 J3 Pin RS 232 1 10 DCD 2 11 RXD 3 12 TXD 4 13 DTR 5 14 Ground 6 15 DSR 7 16 RTS 8 17 CTS 9 18 RI Table 17 COM3 4 Pinout VL CBR 5009 Connectors J5 6 COM3 COM4 J6 Pin J5 Pin RS 232 RS 422 RS 485 1 1 Ground Ground Ground 2 2 RXD RxD RxD 3 3 CTS RxD RxD 4 4 TX...

Page 45: ...mage Table 18 PS 2 Mouse and Keyboard Pinout VL CBR 5009 J4 Top Pin Signal Description 1 MSDATA Mouse Data 2 No Connection 3 GND Ground 4 MKPWR 5 0V Protected 5 MSCLK Mouse Clock 6 No Connection VL CBR 5009 J4 Bottom Pin Signal Description 1 KBDATA Keyboard Data 2 No Connection 3 GND Ground 4 MKPWR 5 0V Protected 5 KBCLK Keyboard Clock 6 No Connection Push Button Reset Connector J13 includes an in...

Page 46: ...or clear bit D7 in I O port 1D0h or 1E0h When changing the register make sure not to alter the values of the other bits The following code examples show how to turn the LED on and off LED On LED Off MOV DX 1D0H MOV DX 1D0H IN AL DX IN AL DX OR AL 80H AND AL 7FH OUT DX AL OUT DX AL Note The LED is turned on by the BIOS during system startup This causes the light to function as a power on indicator ...

Page 47: ...SB3 transmit 6 SATA SATA transmit 7 3 3V 3 3V power 8 5V 5V power 9 USB3RX USB3 receive 10 PERST PERST 11 USB3RX USB3 receive 12 BLADE_REQ BLADE_REQ 13 3 3V 3 3V power 14 SDIO D0 SDIO D0 15 GND Ground 16 SDIO D1 SDIO D1 17 USB USB0 data 18 SDIO D2 SDIO D2 19 USB USB0 data 20 SDIO D3 SDIO D3 21 GND Ground 22 SDIO D4 SDIO D4 23 A_PETp0 Link A lane 0 transmit 24 SDIO D5 SDIO D5 25 A_PETn0 Link A lane...

Page 48: ... by the permanent Master device on board The others are Data In and Data Out with respect to the Master The SPX implementation adds additional features such as chip selects and an interrupt input to the Master The Master device initiates all SPI transactions A slave device responds when its Chip Select is asserted and it receives Clock pulses from the Master The SPI clock rate can be software conf...

Page 49: ... SPILEN1 SPILEN0 Frame Length 0 0 8 bit 0 1 16 bit 1 0 24 bit 1 1 32 bit D3 MAN_SS SPI Manual Slave Select Mode This bit determines whether the slave select lines are controlled through the user software or are automatically controlled by a write operation to SPIDATA3 1DDh If MAN_SS 0 then the slave select operates automatically if MAN_SS 1 then the slave select line is controlled manually through...

Page 50: ..._IRQ_EN Hardware IRQ Enable Enables or disables the use of the selected IRQ IRQSEL by an SPI device 0 SPI IRQ disabled default 1 SPI IRQ enabled Note The selected IRQ is shared with PC 104 ISA bus devices CMOS settings must be configured for the desired ISA IRQ D2 LSBIT_1ST SPI Shift Direction Controls the SPI shift direction of the SPIDATA registers The direction can be shifted toward the least s...

Page 51: ...egister will initiate the SPI clock and if the MAN_SS bit 0 will also assert a slave select to begin an SPI bus transaction Increasing frame sizes from 8 bit use the lowest address for the least significant byte of the SPI data word for example the LSB of a 24 bit frame would be SPIDATA1 Data is sent according to the LSBIT_1ST setting When LSBIT_1ST 0 the MSbit of SPIDATA3 is sent first and receiv...

Page 52: ...handled through CMOS Setup Table 23 Interrupt Configuration default setting allowed setting Source IRQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Timer Keyboard Slave PIC COM1 COM2 COM3 COM4 RTC Mouse Math Chip Pri IDE PCI INTA PCI INTB PCI INTC PCI INTD PCI INTE PCI INTF PCI INTG PCI INTH PCI interrupt routings apply to legacy Programmable Interrupt Controller PIC mode When the OS switches to Advanced...

Page 53: ...A INTB INTC INTD INTE INTF INTG INTH VGA Display High Definition Audio PCIe Port 1 PCIe Port 2 USB UHCI Port 1 USB UHCI Port 2 USB UHCI Port 3 USB UHCI Port 4 USB UHCI Port 5 USB UHCI Port 6 USB EHCI Port 1 USB EHCI Port 2 SATA Ports 0 1 non AHCI SATA Ports 0 1 4 5 AHCI Sata Ports 4 5 non AHCI Intel 82574IT Ethernet ...

Page 54: ...signments Bit Mnemonic Description D7 PLED Light Emitting Diode Controls the programmable LED on connector J13 0 Turns LED on 1 Turns LED off D6 D0 PC Product Code These bits are hard coded to represent the product type The VL EPICs 36 always reads as 0000001 Other codes are reserved for future products PC6 PC5 PC4 PC3 PC2 PC1 PC0 Product Code 0 0 0 0 1 0 0 VL EPICs 36 These bits are read only 7 7...

Page 55: ...its are hard coded to represent the FPGA revision Contact VersaLogic Support for further information These bits are read only D2 EXT Extended Temperature Indicates operating temperature range 0 Standard temperature range 1 Extended temperature range This bit is read only D1 CUSTOM Custom Flag Indicates whether this is a custom FPGA 0 Standard 1 Custom This bit is read only D0 REV Beta Flag Indicat...

Page 56: ...or Jumper Status Indicates the status of the system BIOS selector jumper at V1 1 2 0 Jumper installed backup system BIOS selected 1 No jumper installed primary system BIOS selected This bit is read only D6 BIOS_OR BIOS Jumper Override Overrides the system BIOS selector jumper and selects the BIOS with BIOS_SEL 0 No BIOS override 1 BIOS override D5 BIOS_SEL BIOS Select Selects the system BIOS when ...

Page 57: ...45 Mobile Intel 4 Series Chipset Datasheet Ethernet Controller Intel 82574IT Ethernet Controller Intel 8257IT Datasheet PC 104 Interface PC 104 Specification SUMIT Interface SUMIT Specification General PC Documentation The Programmer s PC Sourcebook Amazon com General PC Documentation The Undocumented PC Amazon com A A ...

Reviews:

No comments

Related manuals for Komodo VL-EPICs-36

Brand: Artesyn Pages: 282

Stellaris RDK-IDM-SBC

Brand: Texas Instruments Pages: 34

Brand: IBASE Technology Pages: 90

Brands by name

0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Popular brands

Load more brands