Interfaces and Connectors
VL-EPICs-36 Reference Manual
27
LVDS
F
LAT
P
ANEL
D
ISPLAY
C
ONNECTOR
(J20)
The integrated LVDS flat panel display interface in the VL-EPICs-36 is an ANSI/TIA/EIA-644-
1995 specification-compliant interface. It can support up to 24 bits of RGB pixel data plus 3 bits
of timing control (HSYNC/VSYNC/DE) on the four differential data output pairs. The LVDS
clock frequency ranges from 25 MHz to 112 MHz.
CMOS Setup provides several options for standard LVDS flat panel types. If these options do not
match the requirements of the panel you are attempting to use, contact
for a custom video BIOS.
The 3.3V power provided to pins 19 and 20 of J20 is protected by a 1 Amp fuse.
Table 6: LVDS Flat Panel Display Pinout
J20
Pin
Signal
Name
Function
1
GND
Ground
2
NC
Not Connected
3
LVDSA3
Diff. Data (+)
4
LVDSA3#
Diff. Data 3 (
-
)
5
GND
Ground
6
LVDSCLK0
Differential Clock (+)
7
LVDSCLK0# Differential Clock (
-
)
8
GND
Ground
9
LVDSA2
Diff. Data 2 (+)
10
LVDSA2#
Diff. Data 2 (
-
)
11
GND
Ground
12
LVDSA1
Diff. Data 1 (+)
13
LVDSA1#
Diff. Data 1 (
-
)
14
GND
Ground
15
LVDSA0
Diff. Data 0 (+)
16
LVDSA0#
Diff. Data 0 (
-
)
17
GND
Ground
18
GND
Ground
19
+3.3V
Protected Power Supply
20
+3.3V
Protected Power Supply
