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After clicking next you will find the project’s settings page. You can use the settings shown below for the Mark 1 board. These
settings can be changed at any time later on. This wizard page is designed to let you choose important software environment settings
from lists of possibilities.
For example, it is on this dialog where you specify what chip you’re designing for, the speed grade, and physical package. You also
set which software
toolchain
and HDL language
you prefer. We’ll touch on what the common tools are and why they are used
shortly.
Figure 8 – Project Settings
The last page is a summary of your chosen settings displayed in plain text. Click Finish and you will be brought into the ISE Project
Navigator development environment. You are now ready to add content to your design.
4.3.
Add Some Logic to Your Project
Take some time to look around the software. The Project Navigator has a clean looking layout and there can be an enormous density
of information displayed at once. Windows users will be familiar with the standard set of menu items located across the top of the
screen; File, Edit, View, Project, Source, Process, Tools, Window, Layout and Help all contain items that fit their respective
categories – as is tradition. The rearrangeable buttons across the top are concise and self-explanatory as well.
In the default workspace view, the top left pane shows the Project’s “Hierarchy.” This tree view shows the relationship between
various HDL modules in the design. You can use this pane to add or remove HDL files from the project.
FPGA are often designed in a tree structure of “modules.” Modules are blocks of logic that
encapsulate
some discrete, unique part of
a design. The blue link describes encapsulation in the context of object-oriented programming but really the term is effective in a
broader sense; HDL modules are can be thought of as “layers” that encapsulate the logic of some abstract but compartmentalized piece
of circuitry. The “top level” module is the “root” of the tree of HDL modules. Although this design will not provide an example of
how to add sub modules to the tree hierarchy, be aware that this is easily done and very common.
Let’s start by adding your design’s top level HDL file.