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IO point is true). And second, the LEDs on the PCB are electrically connected in a positive logic manner (or “
active high
” – when the
LEDOuput0 changes to true, a positive voltage is put on the output pin and current will flow through the LED and illuminate it).
For these reasons, the initial condition for this circuit has LED0 on and LED1 off when PushButton0 is not pressed. When the
module’s input wire, Btn0, changes from true to false because the user pressed PushButton0 on the PCB, the logic shown above will
assign this false input to our LED_reg register on the rising edge of the next OSC_FPGA clock signal.
Finally, because the module logic has used an Assign statement to assign the value of LED_reg to the LEDOutput0 wire and its
inverse to LEDOutput1, you will then see LED0 go dark and LED1 illuminate on the PCB when PushButton0 is pressed.
For more details on how the surrounding hardware is connected to the FPGA consult the
Mark 1 electrical schematic
. For example,
below is the electrical drawing that details the FPGA’s outputs to the bank of LEDs (found on page 5 of the schematic). Clearly, when
the L7 output changes to a logic high level, current will flow through the LED0 to Ground and the LED will illuminate.
Figure 14 – Electrical Drawing of FPGA’s Outputs to Bank of LEDs
To illustrate the inverting nature of our user PushButton0 the following is a drawing of the input circuit (also found on page 5 of the
electrical schematic). You can see that the FPGA’s input, PB0, has a 4.7kOhm “pull-up” resistor attached to it. This means the logic
level on this wire is normally connected to 3.3v which is a logical true. Only when the user presses the button does this input wire’s
voltage level fall to 0v, or false, because the button connects the wire to Ground.
Figure 15 – Electrical Schematic of Active Low Push Button Inputs to FPGA
4.5.
Constraining the Design
In the previous section we described a simple module that turns some LEDs on and off based on the state of an input push button. The
Verilog that describes the circuit is simple. It was entirely defined in one top-level module with two inputs and two outputs. What we
didn’t describe is how this simple design links the module’s inputs and outputs to physical IO points on the FPGA.