ValentFX Mark 1 FPGA Starter Manual Download Page 1 | Manualshive

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ValentFX Mark 1 FPGA Starter Manual Download Page 1

Valent F(x) Logi Family

By Andy Gikling ([email protected])

v1.0 - 6/1/2013

A brief beginner’s guide to the Mark 1 FPGA platform

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Summary of Contents for Mark 1 FPGA

Page 1: ...Valent F x Logi Family By Andy Gikling asgikling gmail com v1 0 6 1 2013 A brief beginner s guide to the Mark 1 FPGA platform...

Page 2: ...nt Environment 5 4 2 Create Your First Project 6 4 3 Add Some Logic to Your Project 7 4 4 So What Does This Simple Program Do 10 4 5 Constraining the Design 11 4 6 Build Your Project 13 4 6 1 Errors 1...

Page 3: ...ock signals to keep things synchronized It s really best to think about the logic on the FPGA s fabric as a physical circuit In computing applications that run on processors people are normally accust...

Page 4: ...of small LEDs A more trained eye will see two SATA headers a JTAG interface and even a small square microcontroller by NPX Semiconductor You will notice a number of other headers on the board The ones...

Page 5: ...ry However these devices are normally called complex programmable logic devices or CPLDs CPLDs differ in several other ways from FGPAs and are designed to do different things than FPGAs Fundamentally...

Page 6: ...dows Explorer to make a new copy of led_counter_i2c_buffered bit If you re using Windows 7 highlighting the file and doing a Copy Paste will generate a copy of the file called led_counter_i2c_buffered...

Page 7: ...ther long document is the official Xilinx Install Guide Consult it if you have problems with the ISE installation When the installation completes open the Xilinx ISE you will most likely find it in yo...

Page 8: ...te Your First Project In this tutorial we will be using the Mark 1 hardware to create a working Verilog HDL design We will keep the physical goals simple in order to demonstrate the basics In the foll...

Page 9: ...rs will be familiar with the standard set of menu items located across the top of the screen File Edit View Project Source Process Tools Window Layout and Help all contain items that fit their respect...

Page 10: ...icking next you are presented with a GUI that lets you define the module s input and outputs It s convenient to think of Verilog HDL modules as chips on a circuit board Typically a chip has a number o...

Page 11: ...s highlighted Things marked in green are comments blue are Verilog language keywords and the pink at the top used to denote the module s timing information for simulating the design we re not going to...

Page 12: ...the module s definition line 29 we ve defined a register that is one bit wide called LED_reg registers like this can be defined as multi bit registers if desired This register can store the state of o...

Page 13: ...the FPGA s outputs to the bank of LEDs found on page 5 of the schematic Clearly when the L7 output changes to a logic high level current will flow through the LED0 to Ground and the LED will illumina...

Page 14: ...o there is a huge amount of information to know surrounding how to constrain designs but fortunately for us our design only needs to constrain a handful of items to work properly this design is so sim...

Page 15: ...see the pins official name next to the input These match what s written in the comments of the constraints file This is common practice For example our design uses LED0 This LED is connected to pin 4...

Page 16: ...process This is because when designs get very large these discrete steps can take hours An engineer would not like to have to re run every step of the compilation process if it s not necessary The fol...

Page 17: ...ages You will find that when you re new to a programming language working through compiler errors teaches you about what s allowed and what s not allowed slowly but effectively However in general it s...

Page 18: ...e there will be many more projects like the above to come If you are a more advanced user you will likely be using a host platform in your design already ValentF x has plans to release an official int...

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