Technical Reference ________________________________________________________________
12 __________________________________________________________________ M210642EN-B
Reset Operation
The master reset signal MRES# from system connector and internal
reset from voltage monitor A1 are connected to the PLD. Internal reset
signal is active if the level of +5 V operating voltage is below 4.65 V.
Both reset signals are combined in PLD and unit reset in MRG112 is
activated if either one input is active.
Back-up Power
The Module uses +5 V operating voltage and in addition the back-up
power +VB is provided for the non-volatile memory of the Module.
The back-up power is supplied by a large capacitor C1, which is
charged to approxi4.2 V from +5 V operating voltage or from
optional stand-by vVSTBY via diodes V5, V10 and V11. The
resistors R18- R20 are for current limiting and the zener diode V9 is
for clamping the maximum capacitor voltage to approximately
+4.2 V.
The typical back-up time with fully charged capacitor is 48 hours and
the time can be made unlimited by using opVSTBY supply.
