Unicorn ENDAT-586EL, User Manual

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User’s Manual 24
PCI Dynamic Bursting
When enabled, data transfers on the PCI bus, where possible. Make sure of the
high performance PCI bust protocol, in which greater amounts of data are
transferred at a single command.
PCI Master 0 WS Write
When enabled, writes to the PCI bus are command with zero wait states.
PCI Delay Transaction
The chipset has an embedded 32 -bit posted write bu ffer to support delay transaction
cycles. Select Enabled to support compliance with PCI specification version 2.1.
PCI IRQ Activated by
This sets the method by which the PCI bus recognizes that IRQ services are being
requested by a device. Under all circumstances, you should retain the default
configuration unless advised otherwise by your system’s manufacturer.