UC-00-M24 EN R2
Hardware
5
Pin definition:
UT4B0 data / power interface is designed with 8 Pin (2 × 4) pins, with a standard
spacing of 2mm.
8
7
6
5
4
3
2
1
Pin Layout
2.1
Pin Definition
No
Pin
I/O
Description
1
ANT_PWR
I
Antenna DC power
2
VCC
I
3.3V DC power
3
TXD
O
Transmit, LVCMOS logic level
4
RST
I
Hardware reset, active low
5
RXD
I
Receive, LVCMOS logic level
6
1PPS
O
1PPS, LVCMOS logic level
7
Reserved/1PPS2
I
Reserved/1PPS2
8
GND
I
Ground
2.2
Electrical Characteristics
Maximum Absolute Rating
Parameter
Symbol
Min
Max
Units
Supply voltage (VCC)
Vcc
-0.3
3.6
V
Input pin voltage
Vin
-0.3
VCC+0.2
V
LNA power supply (antenna)
ANT_PWR
-0.3
6
V
VCC maximum ripple
Vrpp
0
50
mV
Input pin voltage (all other
pins except those mentioned
above)
Vin
-0.3
3.6
V
Maximum ESD Stress
VES (HBM)
± 2000
V
