UC-00-M24 EN R2
Product Introduction
3
1.3
Block Diagram
Figure 1- 2 UT4B0 Structure Diagram
1.
RF
The receiver obtains the filtered and enhanced GNSS signal from the antenna through
the coaxial cable. The RF section converts the RF input signal to IF signal and coverts
the IF analog signal to the digital signal required by NebulasII chip (UC4C0).
2.
NebulasII Chip (UC4C0)
As the new-generation multi-constellation, multi-core high-precision SoC developed
independently by Unicore, NebulasII chip, based on the mature core technology of Nebulas
baseband chips and 55nm low power design, supports 432 hyperchannels. It has built-in
broadband ADC and anti-jamming unit, as well as two integrated 600MHz ARM processors
and a special high-speed floating-point processor to provide more powerful satellite
navigation signal processing capability.
3.
Pulse Per Second (1PPS)
UT4B0 provides one IPPS signal with adjustable output pulse width and polarity.
4.
Reset (RST)
Low active, with retention time no less than 5ms.
RF input
RF
front
end
Interface
