Doc. No: Unex-QSG-21-003
19/23
A printed version of this document is an uncontrolled copy
© 2021 Unex Technology Corporation – Company Confidential
Figure 8: External 1PPS input pins
9.9.
Tamper Detection (Optional)
The tamper detection function will be supported by project base. It is disabled by default.
The tamper detection mechanism is part of the FIPS 140-2 Level 3 security
requirements. The tamper detection itself is carried out entirely in HW. On SW level, there
is only an API that allows enabling the tamper detection mechanism. Calling this API will
move tamper HW state from the testing mode to the production mode. Once called, it
cannot move back to the testing mode.
The source and trigger mode of tamper detection signal can be selected with the DIP
switch on SOM-301(v2)/SOM-351, position SW1.6 and SW1.7.
Tamper detection pins are exposed in both mPCIe interface pin 51 and I/O cable pin 6.
Pulling the tamper detection pin to ground will trigger a tamper event, indicating that the
enclosure of the system has been opened without proper authorization. User can enable
one of the two tamper modes in API:
1
Production mode
2
Test mode.
1PPS (P49)
1
2
3
4
5
6
7
1PPS (P5)
