LISA-U series - System Integration Manual
UBX-13001118 - R17
Advance information
Design-In
Page 128 of 190
2.2
Design Guidelines for Layout
The following design guidelines must be met for optimal integration of LISA-U modules on the final application
board.
2.2.1
Layout guidelines per pin function
This section groups LISA-U modules pins by signal function and provides a ranking of importance in layout
design.
V_BCKP
GND
V_INT
RSVD
GND
GND
GND
DSR
RI
DCD
DTR
GND
RTS
CTS
TXD
RXD
GND
VUSB_DET
PWR_ON
GPIO1
GPIO2
RESET_N
GPIO3
GPIO4
GND
USB_D-
USB_D+
2
3
4
5
6
7
8
9
10
11
12
1
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
GND
VCC
VCC
VCC
GND
SPI_MRDY
SPI_SRDY
SPI_MISO
SPI_MOSI
SPI_SCLK
SPK_N
GND
SPK_P
RSVD
GPIO5
VSIM
SIM_RST
SIM_IO
SIM_CLK
SDA
SCL
I2S_RXD
I2S_CLK
I2S_TXD
I2S_WA
MIC_P
MIC_N
64
63
62
61
60
59
58
57
56
55
54
65
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
29
30
31
32
33
34
35
36
37
38
28
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
75
74
73
72
71
70
69
68
67
66
76
GND
RS
V
D
GND
GND
GND
GND
GND
ANT
GND
GND
GND
LISA-U1 series
(Top View)
V_BCKP
GND
V_INT
RSVD
GND
GND
GND
DSR
RI
DCD
DTR
GND
RTS
CTS
TXD
RXD
GND
VUSB_DET
PWR_ON
GPIO1
GPIO2
RESET_N
GPIO3
GPIO4
GND
USB_D-
USB_D+
2
3
4
5
6
7
8
9
10
11
12
1
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
GND
VCC
VCC
VCC
GND
SPI_MRDY / GPIO14
SPI_SRDY / GPIO13
SPI_MISO
/ GPIO12
SPI_MOSI
/ GPIO11
SPI_SCLK
/ GPIO10
GPIO9 / I2S1_WA
GND
GPIO8 / I2S1_CLK
RSVD /
CODEC_CLK
GPIO5
VSIM
SIM_RST
SIM_IO
SIM_CLK
SDA
SCL
RSVD / I2S_RXD
RSVD / I2S_CLK
RSVD / I2S_TXD
RSVD / I2S_WA
GPIO7 / I2S1_TXD
GPIO6 / I2S1_RXD
64
63
62
61
60
59
58
57
56
55
54
65
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
29
30
31
32
33
34
35
36
37
38
28
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
75
74
73
72
71
70
69
68
67
66
76
GND
GND
GND
GND
GND
GND
ANT
GND
GND
GND
/ R
SV
D
AN
T_
DIV
LISA-U2 series
(Top View)
Very Important
Careful Layout
Common Practice
Legend:
Figure 64: LISA-U1 and LISA-U2 series modules pin-out (top view) with ranked importance for layout design
