LENA-R8 series - System integration manual
UBX-22015376 - R02
Design-in
Page 79 of 116
C1-Public
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The
DSR
and
DCD
pins toggle as output for ~600 ms during the boot of the module cellular system.
The
DSR
and
DCD
pins are also set as output during the firmware update over the USB interface.
Proper precaution must be taken for the
DSR
line if it is connected to an output of an external
device, or if it is grounded. Provide for example an external 100 Ohm series resistor to detach the
output of the module from the output of the external device or the ground.
Additional considerations
If a 3.0 V Application Processor (DTE) is used, the voltage scaling from any 3.0 V output of the DTE to
the corresponding 1.8 V input of the module (DCE) can be implemented, as an alternative low-cost
solution, by means of an appropriate voltage divider. Consider the value of the pull-up integrated at
the input of the module (DCE) for the correct selection of the voltage divider resistance values and
mind that any DTE signal connected to the module must be tri-stated or set low when the module is
in power-down mode and during the module power-on sequence (at least until the activation of the
V_INT
supply output of the module), to avoid latch-up of circuits and allow a proper boot of the module
(see the remark below).
Moreover, the voltage scaling from any 1.8 V output of the cellular module (DCE) to the corresponding
3.0 V input of the Application Processor (DTE) can be implemented by means of a proper low-cost non-
inverting buffer with open drain output. The non-inverting buffer should be supplied by the
V_INT
supply output of the cellular module. Consider the value of the pull-up integrated at each input of the
DTE (if any) and the baud rate required by the application for the appropriate selection of the
resistance value for the external pull-up biased by the application processor supply rail.
☞
Do not apply voltage to any UART interface pin before the switch-on of the UART supply source
(
V_INT
), to avoid latch-up of circuits and allow a proper boot of the module.
☞
The ESD sensitivity rating of the UART pins is 1 kV (HBM according to JESD22-A114). Higher
protection level could be required if the lines are externally accessible, and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG) close to the accessible points.
☞
It is recommended to consider providing accessible test points on the UART
TXD
/
RXD
data lines
and on the AUX UART
DTR
/
DCD
data lines, with a 0
series jumper on each line, to detach the
application processor for diagnostic purposes.
2.6.1.2
Guidelines for UART layout design
The UART
serial interface requires the same considerations regarding electro-magnetic interference
as any other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog
inputs, since the signals can cause the radiation of some harmonics of the digital data frequency.
2.6.2
Cellular USB interface
2.6.2.1
Guidelines for USB circuit design
The
USB_D+
and
USB_D-
lines carry the USB serial data and signaling. USB pull-up or pull-down
resistors and external series resistors on
USB_D+
and
USB_D-
lines as required by the USB 2.0
are part of the module USB pins driver and do not need to be externally provided.
The USB interface of the module is enabled if a valid high logic level is detected by the
VUSB_DET
input of the module (see the LENA-R8 series data sheet
). Neither the USB interface, nor the whole
module is supplied by the
VUSB_DET
input, which senses the voltage and absorbs few microamperes.
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The
USB_BOOT
input pin has to be set high, at the 1.8 V voltage level of the
V_INT
supply output,
to enable the FW update by means of the dedicated tool over the USB interface of the LENA-R8
series modules
’
cellular system.
