NORA-W2 series - Hardware integration manual
UBX-22005177 - R01
Design-in
Page 25 of 61
C1
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Public
3.7
Design-in checklists
3.7.1
Schematic checklist
All module pins have been properly numbered and designated in the schematic (including thermal
pins).
Power supply design complies with the specification.
The power sequence has been properly implemented.
Adequate bypassing has been included in front of each power pin.
Each signal group is consistent with its own power rail supply or proper signal translation has been
provided.
Configuration pins are properly set at bootstrap.
SDIO bus includes series resistors and pull-ups, if needed.
Unused pins are properly terminated.
A pi-filter is provided in front of each antenna for final matching.
Additional RF co-location filters have been considered in the design.
3.7.2
Layout checklist
PCB stack-up and controlled impedance traces follow the recommendations given by the PCB
manufacturer.
All pins are properly connected, and the footprint follows u-blox pin design recommendations.
Proper clearance has been provided between the RF and digital sections of the design.
Proper isolation has been provided between antennas (RF co-location, diversity, or multi-antenna
design).
Bypass capacitors have been placed close to the module.
Low impedance power path has been provided to the module.
Controlled impedance traces have been properly implemented in the layout (both RF and digital)
and the recommendations provided by the PCB manufacturer have been followed.
50
Ω
RF traces and connectors follow the rules described in
Antenna interfaces
.
Antenna design has been reviewed by the antenna manufacturer.
Proper grounding has been provided to the module for the low impedance return path and heat
sink.
All traces and planes are routed inside the area defined by the main ground plane.
u-blox has reviewed and approved the PCB
3
.
3
This is applicable only for end-products based on u-blox reference designs.