NINA-B4 series - System integration manual
UBX-19052230 - R06
Design-in
Page 24 of 45
C1-Public
Figure 9 shows the pinout of the 10-pin, 50 mil pitch connector used on the EVK-NINA-B40x. This
compact debug header can also be used on a host board design. Other solutions, such as test points
or spring-loaded connectors (Tag-Connect-pads [19]), can be used as well. Keep in mind that the
GND
and
VDD_IO
references are needed for the SWD interface to work.
Figure 10: Cortex debug connector pin out for SWD
2.6
General layout guidelines
The best practices described in sections 2.6.1 to 2.6.4 are valid for any bus in NINA-B4 series modules.
2.6.1
General considerations for schematic design and PCB floor-planning
•
Low frequency signals are generally not critical to the layout and designers should focus on the
higher speed buses. One exception to this general rule is when high impedance traces (such as
signals driven by weak pull resistors) might be affected by crosstalk. For these and similar traces,
a supplementary isolation of 4w (four times the line width) from other buses is recommended.
•
Verify which interface bus requires termination and add series resistor terminations to these
buses.
•
Carefully consider the placement of the module with respect to antenna position and host
processor.
•
Verify the controlled impedance dimensions of the selected PCB stack-up. The PCB manufacturer
might be able to provide test coupons.
•
Verify that the power supply design and power sequence are compliant with NINA-B4 series
module specifications, as described in the respective NINA-B4 data sheet [2][3].
⚠
Take particular care not to place components close to the antenna area. Follow the
recommendations from the antenna manufacturer to determine the safe distance between the
antenna and any other part of the system. Designers should also maximize the distance between
the antenna and high-frequency buses, like DDRs and related components, or consider the use of
an optional metal shield to reduce potential interference picked up by the module antenna.
2.6.2
Layout and manufacturing
•
An optimized module placement provides for better RF performance. See also section 2.3.2.
•
Bypass capacitors should be placed as close as possible to the module. Prioritize the placement of
capacitors with the least capacitance so that these are closest to module pads. The supply rails
must be routed through the capacitors from the power supply to the supply pad on the module.
•
Avoid stubs and through-hole vias on high-speed signals which might adversely affect signal
quality.
•
Verify the recommended maximum signal skew for differential pairs and length matching of
buses.
•
Minimize the routing length. Ensure that the maximum allowable length for high-speed buses is
not exceeded. Longer traces generally degrade signal performance.
