LARA-R2 series - System Integration Manual
UBX-16010573 - R02
Objective Specification
System description
Page 12 of 148
Function
Pin Name
Pin No
I/O
Description
Remarks
SIM
VSIM
41
O
SIM supply output
VSIM
= 1.8 V / 3 V output as per the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_IO
39
I/O
SIM data
Data input/output for 1.8 V / 3 V SIM
Internal 4.7 k
pull-up to
VSIM
.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_CLK
38
O
SIM clock
3.25 MHz clock output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_RST
40
O
SIM reset
Reset output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
UART
RXD
13
O
UART data output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24,
for AT commands, data communication, FOAT, FW update
by u-blox EasyFlash tool and diagnostic.
Test-Point and series 0
for diagnostic access recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
TXD
12
I
UART data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
for AT commands, data communication, FOAT, FW update
by u-blox EasyFlash tool and diagnostic.
Internal active pull-up to
V_INT
.
Test-Point and series 0
for diagnostic access recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
CTS
11
O
UART clear to send
output
1.8 V output, Circuit 106 (CTS) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RTS
10
I
UART ready to send
input
1.8 V input, Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to
V_INT
.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DSR
6
O
UART data set ready
output
1.8 V output, Circuit 107 (DSR) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RI
7
O
UART ring indicator
output
1.8 V output, Circuit 125 (RI) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DTR
9
I
UART data terminal
ready input
1.8 V input, Circuit 108/2 (DTR) in ITU-T V.24.
Internal active pull-up to
V_INT
.
Test-Point and series 0
for diagnostic access recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DCD
8
O
UART data carrier
detect output
1.8 V input, Circuit 109 (DCD) in ITU-T V.24.
Test-Point and series 0
for diagnostic access recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
