GPS Receiver A1030-A
12.10.3 HDLC
The HDLC interface supports both the Telepass protocol and the European TC278
DSRC communication standard. It supports Full Duplex operating mode with inde-
pendent baudrates for transmit/receive, including PLL for clock recovery. It features
NRZ, NRZI, Manchester encoding, automatic bit stuffing, FCS generation and CRC
check. Packets are stored in a local dual-port memory, for later retrieval by the
CPU; this buffer is sized to hold a full HDLC frame, to minimize CPU load during the
transaction.
A1030A
: The HDLC interface pins are realized in the following way:
25: P1.4 - Transmit Buffer Active
27: P1.5 - Oversampling Clock Out
20: P1.13 - Reference Clock
22: P1.14 - Receiver Data Input
24: P1.15 - Transmit Data Output
12.10.4 CAN
The C-CAN consists of the components CAN Core, Message RAM, Message Han-
dler, Control Registers, and Module Interface. The CAN Core performs communica-
tion according to the CAN protocol version 2.0 part A and B. The bit rate can be
programmed to values up to 1MBit/s. For the connection to the physical layer addi-
tional transceiver hardware is required. For communication on a CAN network, indi-
vidual Message Objects are configured. The Message Objects and Identifier Masks
for acceptance filtering of received messages are stored in the Message RAM.
All functions concerning the handling of messages are implemented in the Message
Handler. Those functions are the acceptance filtering, the transfer of messages be-
tween the CAN Core and the Message RAM, and the handling of transmission re-
quests as well as the generation of the module interrupt. The register set of the C-
CAN can be accessed directly by the CPU via the module interface. These registers
are used to control/configure the CAN Core and the Message Handler and to ac-
cess the Message RAM.
A1030A
: The CAN signals CAN-TX and CAN-RX are realized on pins 18 and 16,
respectively.
12.10.5 USB Slave Interface
The USB_IP Peripheral provides an USB compliant connection between the host
PC and the function implemented inside the ARM device. Data transfers between
host PC and system memory occur through a dedicated packet buffer memory ac-
cessed directly by the USB_IP peripheral. This dedicated buffer memory must be
sized according to the number of used endpoints and their related maximum packet
sizes. In this implementation the dedicated memory is sized to 512 Byte and up to 8
V2.0 - 07/05
User’s Manual
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