TYAN Transport GX28 B2881, User Manual

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ECC configuration submenu
Use this menu to view and make changes to the ECC (Error
Correcting Code) setup for system and DRAM.
Feature Option Description
Memory configuration
Bank Interleaving
• Disabled
• Enabled
Allows memory access to be spread
across memory banks.
Node Interleaving • Disabled
• Enabled
Allows memory access to be spread
across memory nodes.
Burst length • 8 beats
• 4 beats
Burst length must be set to 8 beats
for 128 bit memory support.
Main Advanced PCI/PnP Boot Security Chipset Power Exit
Memory Configuration
Use [Enter], [TAB] or
[SHIFT_TAB] to select
a field
Use [+] or [-] to config-
ure system time.
Select Screen
Select item
+/- Change option
Tab Select field
F1 General Help
F10 Save and Exit
ESC Exit
Master ECC
DRAM ECC
L2 Cache BG Scrub
Data Cache BG Scrub [Enabled]
[Disabled]
[Disabled]
[Disabled]
Feature Option Description
ECC Configuration
Master ECC
• Enabled
• Disabled
Enables support on all nodes for ECC
error checking and correction.
DRAM ECC • Disabled
• Enabled
Enables support on all banks for ECC
error checking and correction.
L2 cache BG
Scrub • Disabled
• Enabled
Enables support for ECC when L2
cache is idle.
Data cache BG
Scrub • Disabled
• Enabled
Enables support for ECC when L1
cache is idle.