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3.3.1 Advanced Chipset Control
This section allows you to fine tune the chipset configuration.
PhoenixBIOS Setup Utility
Main
Advanced
Power Boot Exit
Advanced Chipset Control
Item Specific Help
X
ICH USB Control Sub-Menu
X
LAN Control Sub-Menu
Crystal Beach Configure Enable
SERR signal condition
4GB PCI Hole Granularity
Memory Branch Mode
Branch 0 Rank Sparing
Branch 1 Rank Sparing
Enhanced x8 Detection
WatchDog Timer
Enable Multimedia Timer
Parallel ATA:
Serial ATA:
Native Mode Operation:
SATA Controller Mode Option
[Enabled]
[Single bit]
[256 MB ]
[Interleave]
[Disabled]
[Disabled]
[Enabled]
[Disabled]
[No]
[Enabled]
[Enabled]
[Auto]
[Compatible]
These items control
various ICH USB device
F1
Help
↑↓
Select Item
-/+
Change Values
F9
Setup Defaults
Esc
Exit
←
→
Select Menu
Enter
Select
X
Sub-Menu
F10
Previous Values
Crystal Beach Configure Enable
This feature is used to enable/disable the Crystal Beach.
Disabled /
Enabled
SERR signal condition
Select ECC error conditions that SERR# be asserted.
None /
Single bit
/ Multiple bit/ Both
4GB PCI Hole Granularity
This feature is used to select the granularity of PCI hole for PCI resource. If MTRRs are
not enough, we may use this option to reduce the MTRR occupation.
256MB
/ 512MB / 1.0GB / 2.0GB
Memory Branch Mode
This option is used to select the type of memory operation mode.
Interleave
/ Sequential / Mirror
Branch 0 Rank Sparing
This option is used to enable/disable Branch 0 rank/DIMM sparing feature.
