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3.7.3.1.3 GPP1/GPP2/GPP3a/GPP3b Core Setting
BIOS Setup Utility
Main Advanced PCI/PnP Boot Security
Chipset
Exit
Turn Off PLL During L1/L23
TXCLK Clock Gating in L1
LCLK Clock Gating in L1
[Enabled]
[Enabled]
[Enabled]
Enabled
Disabled
←
Select Screen
↑↓
Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
Turn Off PLL During L1/L23
Enabled
/ Disabled
TXCLK Clock Gating in L1
Enabled
/ Disabled
LCLK Clock Gating in L1
Enabled
/ Disabled
3.7.3.1.4 SB Core Setting
BIOS Setup Utility
Main Advanced PCI/PnP Boot Security
Chipset
Exit
TXCLK Clock Gating in L1
LCLK Clock Gating in L1
[Enabled]
[Enabled]
Enabled
Disabled
←
Select Screen
↑↓
Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
TXCLK Clock Gating in L1
Enabled
/ Disabled
LCLK Clock Gating in L1
Enabled
/ Disabled
Summary of Contents for S8226
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Page 11: ...http www tyan com 11 2 2 Block Diagram S8226 Block Diagram...
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Page 20: ...http www tyan com 20 JP5 JP1 JP2 JP4 J10...
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