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IRQ
An Interrupt Request is an electronic request that runs from a hardware
device to the CPU. The interrupt controller assigns priorities to incoming
requests and delivers them to the CPU. It is important that there is only one
device hooked up to each IRQ line; doubling up devices on IRQ lines can lock
up your system. Happily, Plug and Play operating systems take care of these
details for you.
ISA
stands for
I
ndustry
S
tandard
A
rchitecture. ISA is a slower 8- or 16-bit
BUS (data pathway).
Latency
is the amount of time that one part of a system spends waiting for
another part to catch up. This is most common when the system sends data
out to a peripheral device, and is waiting for the peripheral to send some data
back (peripherals tend to be slower than onboard system components).
NVRAM
ROM and EEPROM are both examples of
N
on-
V
olatile
RAM
, memory
that holds its data without power. DRAM, in contrast, is volatile.
OEMs
(
O
riginal
E
quipment
M
anufacturers) like Compaq or IBM package other
companies motherboards and hardware inside their case and sell them.
The
parallel port
transmits the bits of a byte on eight different wires at the
same time (that is, in parallel form, eight bits at the same time).
PCI
stands for
P
eripheral
C
omponent
I
nterconnect. PCI is a 32-bit local bus
(data pathway) which is faster than the ISA bus. Local buses are those which
operate within a single system (as opposed to a network bus, which connects
multiple systems).
The
PCI PIO
(
PCI
P
rogrammable
I
nput/
O
utput) modes are the data transfer
modes used by IDE drives. These modes use the CPU for data transfer (DMA
channels do not). PCI refers to the type of bus used by these modes to
communicate with the CPU.
PCI-to-PCI bridge
allows you to connect multiple PCI devices onto one PCI
slot.
Pipeline burst SRAM
is a fast secondary cache. It is used as a secondary
cache because SRAM is slower than SDRAM, but usually larger. Data is
cached first to the faster primary cache, and then, when the primary cache is
full, to the slower secondary cache.
Appendix
Glossary
