Trenz Electronic TEI0015 08-C8A Series, Schematics

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Date: Page 3 of 10
Number:
Title:
FPGA MISC
02
Rev.
A4
Copyright: Trenz Electronic GmbH
FPGA_MISC.SchDoc
Filename:
2019-07-16
08-C8A
TEI0015
Drawn by: VY
BANK 1A
BANK 1B
IO_1A/ADC1IN1/DIFFIO_RX_L1N
D1
IO_1A/ADC1IN2/DIFFIO_RX_L1P
C2
IO_1A/ADC1IN3/DIFFIO_RX_L3N
E3
IO_1A/ADC1IN4/DIFFIO_RX_L3P
E4
IO_1A/ADC1IN5/DIFFIO_RX_L5N
C1
IO_1A/ADC1IN6/DIFFIO_RX_L5P
B1
IO_1A/ADC1IN7/DIFFIO_RX_L7N
F1
IO_1A/ADC1IN8/DIFFIO_RX_L7P
E1
IO_1B/DIFFIO_RX_L14N
F4
IO_1B/DIFFIO_RX_L14P
G4
IO_1B/DIFFIO_RX_L16N
H2
IO_1B/DIFFIO_RX_L16P
H3
ADC_VREF
D3
IO_1B/JTAGEN
E5
IO_1B/TMS/DIFFIO_RX_L11N
G1
IO_1B/TCK/DIFFIO_RX_L11P
G2
IO_1B/TDI/DIFFIO_RX_L12N
F5
IO_1B/TDO/DIFFIO_RX_L12P
F6
ANAIN1
D2
REFGND
E2
VREFB1N0
H1
VCCIO1A
F2
VCCIO1B
G3
U1A
10M08SAU169C8G
GND
N13
GND
N1
GND
M6
GND
L9
GND
J4
GND
H12
GND
G7
GND
F3
GND
E11
GND
D5
GND
C3
GND
B8
GND
A13
GND
A1
VCCA1
K4
VCCA2
D10
VCCA3
D4
VCCA4
K9
VCC_ONE
H7
VCC_ONE
G8
VCC_ONE
G6
VCC_ONE
F7
U1G
10M08SAU169C8G
GND
3.3V
3.3V
TMS
TDI
TDO
TCK
6.3V
X5R
C2
4.7µF
25V
X5R
C3
100nF
25V
X5R
C4
100nF
25V
X5R
C10
100nF
GND
25V
X5R
C32
100nF
GND
3.3V
1%
R21 12K
JTAGEN
i
JTAG
LEFT LS
BANK 8
IO_8/DIFFIO_RX_T14P
C10
IO_8/DIFFIO_RX_T15P
A8
IO_8/DIFFIO_RX_T14N
C9
IO_8/DIFFIO_RX_T15N
A9
IO_8/DIFFIO_RX_T16P
B10
IO_8/DIFFIO_RX_T17P
A10
IO_8/DIFFIO_RX_T17N
A11
IO_8/DIFFIO_RX_T18N
E8
IO_8/DIFFIO_RX_T19P
A7
IO_8/DIFFIO_RX_T19N
A6
IO_8/DIFFIO_RX_T20P
B6
IO_8/DIFFIO_RX_T21P
A4
IO_8/DIFFIO_RX_T20N
B5
IO_8/DIFFIO_RX_T21N
A3
IO_8/DIFFIO_RX_T22P
E6
IO_8/DIFFIO_RX_T23P
B3
IO_8/DIFFIO_RX_T23N
B4
IO_8
A5
IO_8/DIFFIO_RX_T26P
A2
IO_8/DIFFIO_RX_T26N
B2
VREFB8N0
B7
IO_8/DEV_CLRN/DIFFIO_RX_T16N
B9
IO_8/DEV_OE/DIFFIO_RX_T18P
D8
IO_8/CONFIG_SEL
D7
I_8/NCONFIG
E7
IO_8/CRC_ERROR/DIFFIO_RX_T22N
D6
IO_8/NSTATUS/DIFFIO_RX_T24P
C4
IO_8/CONF_DONE/DIFFIO_RX_T24N
C5
VCCIO8
C8
VCCIO8
C7
VCCIO8
C6
U1F
10M08SAU169C8G
3.3V
25V
X5R
C29
100nF
GND
1%
R3
12K
1%
R5
12K
3.3V
3.3V
BDBUS1
BDBUS2
BDBUS3
BDBUS0
DEVCLRN
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
NCONFIG
F_CS
F_CLK
F_DI
F_DO
CONF_DONE
1%
R20 12K
3.3V
1%
R22 12K
3.3V
RESET
1%
R26
330R
GND
BDBUS4
BDBUS5
25V
X5R
C25
100nF
GND
USER_BTN
1%
R34 12K
3.3V
TOP LS
NSTATUS
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AREF
1%
R56
1R
25V
X5R
C15
100nF
GND
3.3V
BANK1B not useable when ADC is enabled
AIN
GND
PCB_REV_BIT_0