Chipset Configuration Setup
BXT7059 / BXTS7059 Technical Reference
South Bridge Configuration (continued)
PCI Express Ports
Configuration
These settings are available for configuring the PCI Express links used for
component interconnects on the board and for the B0 PCIe link routed to the
SHB’s edge connector. The default setting for each port is set to Auto and
Trenton highly recommends leaving these settings alone. These internal PCIe
ports drive on-board components and turning them off will disable critical SHB
and system functions
The available options include:
PCI Express Port 1:
Disabled, Enabled, Auto
PME SCI:
Disabled, Enabled
PCI Express Port 2:
Disabled, Enabled, Auto
PME SCI:
Disabled, Enabled
PCI Express Port 3:
Disabled, Enabled, Auto
PME SCI:
Disabled, Enabled
PCI Express Port 4:
Disabled, Enabled, Auto
PME SCI:
Disabled, Enabled
PCI Express Port 5:
Disabled, Enabled, Auto
PME SCI:
Disabled, Enabled
PCI Express Port 6:
Disabled, Enabled, Auto
PME SCI:
Disabled, Enabled
PCI Express Port 7:
Disabled, Enabled, Auto
PME SCI:
Disabled, Enabled
PCI Express Port 8:
Disabled, Enabled, Auto
PME SCI:
Disabled, Enabled
PCI Sub Decode
Disabled
/Enabled – If enabled the following sub-menus selection appears.
Port Select:
PCI Express Port 1
,
PCI Express Port 2
,
PCI Express Port 3
,
PCI
Express Port 4
,
PCI Express Port 5
,
PCI Express Port 6
,
PCI Express Port 7
,
PCI Express Port 8
DMI Vc1 Control
Disabled/
Enabled
DMI Vcp Control
Disabled/
Enabled
USB Configuration
This option allows the user to
Enable
or Disable the various USB ports inside
the Intel® C604 PCH. These internal USB ports drive the USB interface
connections to the SHBs I/O plate and down to edge connector C for us on a
PICMG 1.3 backplane.
The available option parameters include:
EHCI Controller 1:
Disabled/Enabled
EHCI Controller 2:
Disabled/Enabled
USB Port #:
Disabled/Enabled
Note: # equals the USB port number of 1 through 13
Intel ME Subsystem
Configuration
The Intel® Management Engine or Intel® ME is a portion of the Intel® C604
firmware stored in the boards SPI devices and is used in conjunction such
features Intel® AMT and the PCI Express GEN3 link parameters. Exercise
caution if you elect to change the following default parameters:
ME Sub System:
Disabled/Enabled
ME Temporary Disable:
Disabled/ Enabled
End of Post Message:
Disabled/Enabled
Execute MEBx:
Disabled/Enabled
Trenton
Systems
Inc.
3-4
