T
T
T
S
S
S
6
6
6
4
4
4
G
G
G
S
S
S
S
S
S
D
D
D
1
1
1
0
0
0
-
-
-
M
M
M
1.0” Solid State Disk
Transcend Information Inc.
V1.6
14
NOTES:
1 Device address comprises CS1#, CS0#, and HA [2:0].
2 Data comprises HD [15:] (16-bit) or HD [7:0] (8 bit).
3 The negation of DSTROBE by the device is used to lengthen the PIO cycle. Whether the cycle is to be extended is
determined by the host after t
A
from the assertion of HIOR# or HIOW#. The assertion and negation of DSTROBE is
described in the following three cases:
(a) The device never negates DSTROBE: No wait is generated.
(b) Device drives DSTROBE low before t
A
: a wait is generated. The cycle is completed after DSTROBE is reasserted.
For cycles in which a wait is generated and HIOR# is asserted, the device places read data on D15-D00 for t
RD
before DSTROBE is asserted.
