Transcend TS64GSSD10-M Specification Download Page 3

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1.0” Solid State Disk

Transcend Information Inc.

V1.6

* Note : 25

℃

, test on ASUS M3N7B, 3GB RAM, IDE interface support UDMA5, Windows

XP SP3, benchmark utility

FDBENCH (version 1.02), copied file 100MB

Actual Capacity

Model P/N

User LBA

Cylinder

Head

Sector

TS64GSSD10-M

125,059,072

16383

* Note: FAT32 format

Reliability

Data Reliability

Random 8-bit BCH ECC in 512 bytes

Data Retention

10 years [7 years operating (block erase cycle < 4K cycle) + 3 years storage]

Connector Durability

10 times

MTBF

4,400,000 hours

Interface Specification

Drivers

No Device Driver Required

ATA-7 V3 Specification

PIO Mode 0 - 4

Multi-Word DMA Mode 0 -2

ATA Compatibility

UDMA Mode 0 - 5

Performance

Model P/N

Capacity

Read

Write

Random Read

Random Write

PCMark05

HDD Score

TS64GSSD10-M

64GB

64851

39233

56952

11297

6358

Regulations

Compliance

CE, FCC and BSMI

Summary of Contents for TS64GSSD10-M

Page 1: ...ur device or system Placement Features RoHS compliant Fully compatible with 1 0 inch hard drive form factor and interface 35 Pin FPC ZIF connector Non volatile Flash Memory for outstanding data retent...

Page 2: ...Form Factor 1 inch HDD Storage Capacities 64 GB Length 30 0 0 0 20 Width 40 00 0 30 Dimensions mm Height 5 00 0 50 Weight 8 g Connector 0 3 mm pitch 35 Pin Zero Insertion Force ZIF connector P ATA Env...

Page 3: ...Note FAT32 format Reliability Data Reliability Random 8 bit BCH ECC in 512 bytes Data Retention 10 years 7 years operating block erase cycle 4K cycle 3 years storage Connector Durability 10 times MTBF...

Page 4: ...4G G GS S SS S SD D D1 1 10 0 0 M M M 1 0 Solid State Disk Transcend Information Inc V1 6 9 Mechanical Dimensions Below figure illustrates the Transcend 1 Solid State Disk All dimensions are in mm Top...

Page 5: ...gnments Pin No Pin Name Pin No Pin Name 01 GND 02 DD10 03 DD9 04 DD2 05 DD8 06 DD1 07 PDIAG 08 DD0 09 DASP 10 DA0 11 DMACK 12 DA1 13 DMARQ 14 DA2 15 DSTROBE 16 RESET 17 CSEL 18 VCC 19 VCC 20 INTRQ 21...

Page 6: ...ow level output voltage VOL 0 8 V 2 4 V Non schmitt trigger High level input voltage VIH 2 05 V Schmitt trigger 1 0 6 V Non schmitt trigger Low level input voltage VIL 1 25 V Schmitt trigger 1 Pull up...

Page 7: ...m 33 ohm DMARQ 82 ohm 22 ohm INTRQ 82 ohm 22 ohm DSTROBE DDMARDY DSTROBE 82 ohm 22 ohm RESET 33 ohm 88 ohm NOTE Only those signals requiring termination are listed in this table If a signal is not lis...

Page 8: ...e t0 denotes the minimum total cycle time t2 represents the minimum command active time and t2i is the minimum command recovery time or command inactive time Actual cycle time equals the sum of the ac...

Page 9: ...hether the cycle is to be extended is determined by the host after tA from the assertion of HIOR or HIOW The assertion and negation of DSTROBE is described in the following three cases a The device ne...

Page 10: ...HIOW asserted width min 215 80 70 1 tE HIOR data access max 150 60 50 tF HIOR data hold min 5 5 5 tG HIOR HIOW data setup min 100 30 20 tH HIOW data hold min 20 15 10 tI DMACK to HIOR HIOW setup min...

Page 11: ...6 16 Initiating a Multiword DMA data burst NOTE The host shall not assert DMACK or negate both CS0 and CS1 until the assertion of DMARQ is detected The maximum time from the assertion of DMARQ to the...

Page 12: ...e Device shall negate DMARQ within the tL of the assertion of the current HIOR or HIOW pulse The last data word for the burst shall then be transferred by the negation of the current HIOR or HIOW puls...

Page 13: ...te the transmission of a data burst the host shall negate DMACK within tJ after a HIOR or HIOW pulse No further HIOR or HIOW pulses shall be asserted for this burst 2 If the device is able to continue...

Page 14: ...MA Mode 2 UDMA Mode 3 UDMA Mode 4 UDMA Mode 5 Min Max Min Max Min Max Min Max Min Max Min Max Measure location see Note 2 t2CYCTYP 240 160 120 90 60 40 Sender tCYC 112 73 54 39 25 16 8 Note 3 t2CYC 23...

Page 15: ...RC valid until DMACK negation 3 tCVH CRC word valid hold time at sender from DMACK negation until CRC may become invalid 3 tZFS Time from STROBE output released to driving until the first transition o...

Page 16: ...f the cable only in a configuration with a single device located at the end of the cable This could result in the minimum values for tDS and tDH for mode 5 at the middle connector being 3 0 and 3 9 ns...

Page 17: ...M M 1 0 Solid State Disk Transcend Information Inc V1 6 22 Initiating an Ultra DMA data in burst Note The definitions for the HIOW STOP HIOR HDMARDY HSTROBE and DSTROBE DDMARDY DSTROBE signal lines a...

Page 18: ...TOP HIOR HDMARDY HSTROBE and DSTROBE DDMARDY DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Host pausing an Ultra DMA data in burst Note 1 The host may assert STOP to reques...

Page 19: ...1 10 0 0 M M M 1 0 Solid State Disk Transcend Information Inc V1 6 24 Device terminating an Ultra DMA data in burst Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in...

Page 20: ...1 1 10 0 0 M M M 1 0 Solid State Disk Transcend Information Inc V1 6 25 Host terminating an Ultra DMA data in burst Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in...

Page 21: ...MARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Sustained Ultra DMA data out burst Note DD 15 0 and HSTROBE signals are shown at both the device and the host to emp...

Page 22: ...formation Inc V1 6 27 Device pausing an Ultra DMA data out burst Note 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated 2 After ne...

Page 23: ...1 10 0 0 M M M 1 0 Solid State Disk Transcend Information Inc V1 6 28 Host terminating an Ultra DMA data out burst Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in...

Page 24: ...1 10 0 0 M M M 1 0 Solid State Disk Transcend Information Inc V1 6 29 Device terminating an Ultra DMA data out burst Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in...

Page 25: ...y Management Read Keying Material B9 Feature 80 Y Y Y Y Y NOT Support 1 12 Key Management Change Key Management Value B9 Feature 81 Y Y Y Y Y NOT Support 1 13 NOP 00h Y Support 14 Read Buffer E4h Y Su...

Page 26: ...C5h Y Y Y Y Y Support 40 Write Multiple w o Erase CDh Y Y Y Y Y Support 41 Write Sector s 30h or 31h Y Y Y Y Y Support 42 Write Sector s w o Erase 38h Y Y Y Y Y Support 43 Write Verify 3Ch Y Y Y Y Y S...

Page 27: ...off line data collection activity 366 X Vendor specific 367 F Off line data collection capability 368 369 F SMART capability 370 F Error logging capability 7 1 Reserved 0 1 Device error logging suppo...

Page 28: ...The Sector Count register shall specify the number of sectors to be read from the log number specified by the LBA Low register It should specify 4 It can record 256 new bad blocks information in this...

Page 29: ...ar drive Word Address Default Value Total Bytes Data Field Type Information 0 044Ah 2 General configuration bit Significant 1 3FFFh 2 16383 Default number of cylinders 2 0000h 2 Reserved 3 000Fh 2 15...

Page 30: ...for SATA Capabilities SATA interface 0006h IDE interface 0000h 77 79 0000h 6 Reserved 80 0080h 2 Support ATA ATAP1 7 81 0000h 2 Minor version numner 82 742Bh 2 Features command sets supported 83 5100...

Page 31: ...T T TS S S6 6 64 4 4G G GS S SS S SD D D1 1 10 0 0 M M M 1 0 Solid State Disk Transcend Information Inc V1 6 36 165 175 0000h 22 Reserved 176 255 0000h 140 Reserved...

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