•••••
CPU to PCI Write Buffer
If “Enabled” is selected, writes from the CPU to the PCI bus are buffered to compensate
for the speed differences between the CPU and the PCI bus. If “Disabled”, the writes
are not buffered and the CPU must wait until the write is complete before starting
another write cycle.
•
PCI Dynamic Bursting
When “Enabled”, every write transaction goes to the write buffer. Burstable transactions
then burst on the PCI bus and nonburstable transactions will write to PCI bus immediately.
•
PCI Master 0 WS Write
When “Enabled”, writes to the PCI bus are executed with zero wait states.
•
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transaction
cycles. Select “Enabled” to support compliance with PCI specification version 2.1.
•
PCI #2 Access #1 Retry
Select “Enabled” to support PCI #2 (AGP bus) access to PCI #1 (PCI bus) retry function
when a error occurrs. The default value is “Disabled”.
•
AGP Master 1 WS Write
Selecting “Enabled” will implement a single delay when writing to the AGP Bus. By
default, two wait states are used by the system, allowing for greater stability.
•
AGP Master 1 WS Read
This implements a single delay when reading to the AGP Bus. By default, two-wait
states are used by the system, allowing for greater stability.
BIOS SETUP
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