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T

T

T

S

S

S

2

2

2

G

G

G

S

S

S

D

D

D

1

1

1

5

5

5

0

0

0

 

 

 

                           

2GB 150x Secure Digital Card

 
 

Transcend Information Inc.

 

 

9

4. Relative Card Address Register (RCA) 

The writable 16-bit relative card address register carries the card address assigned by the host during the card 
identification. This address is used for the addressed host-card communication after the card identification procedure. 
The default value of the RCA register is 0x0001. The value 0x0000 is reserved to set all cards into the Stand-by State 
with CMD7. In SD mode, the value of this register is generated by random number generator inside the card. Please 
reference to SD specification for detail information. 

 

5. Card Specific Data Register (CSD) 

The Card-Specific Data register provides information on how to access the card contents. The CSD defines the data 
format, error correction type, maximum data access time, data transfer speed, whether the DSR register can be used 
etc. The programmable part of the register can be changed by CMD27. 

CSD bit 

Width 

Name 

Field 

Value 

Note 

[127:126] 2 

CSD 

structure 

CSD_STRUCTURE 00 

b  v1.0 

[125:120] 6 

Reserved 

--- 

--- 

--- 

[119:112] 

Data read access-time 1 

TAAC 

7F h 

80 ms 

[111:104] 

Data read access-time 2 

NSAC 

FF h 

25.5k clocks 

[103:96] 

Max. bus clock freq. 

TRAN_SPEED 

32 h 

25 MHz 

[95:84] 

12 

Card command classes 

CCC 

1F5 h 

(*1) 

[83:80] 

Max. read data block length

READ_BL_LEN 

9 h 

512 bytes 

[79] 

Partial block read allowed 

READ_BL_PARTIAL 

1 b 

Support 

[78] 

Write block misalignment 

WRITE_BLK_MISALIGN 

1 b 

Support 

[77] 

Read block misalignment 

READ_BLK_MISALIGN 1 

b  Support 

[76] 

DSR implemented 

DSR_IMP 

0 b 

Not support 

[75:74] 2 

Reserved 

--- 

--- 

--- 

[73:62] 12 

Device 

size 

C_SIZE 

(*2) 

(*2) 

[61:59] 

Max. R_curr @ 

VDD 

min 

VDD_R_CURR_MIN 

101 b 

35 mA 

[58:56] 

Max R_curr @ 

VDD 

max 

VDD_R_CURR_MAX 

101 b 

45 mA 

[55:53] 

Max W_curr @ 

VDD 

min 

VDD_W_CURR_MIN 

101 b 

35 mA 

[52:50] 

Max W_curr @ 

VDD 

max 

VDD_W_CURR_MAX 

101 b 

45 mA 

[49:47] 

Device size multiplier 

C_SIZE_MULT 

(*2) 

(*2) 

[46] 

Erase single block enable 

ERASE_BLK_EN 

0 b 

Not allowed 

[45:39] 

Erase sector size 

SECTOR_SIZE 

(*3) 

(*3) 

[38:32] 

Write protect group size 

WP_GRP_SIZE 

(*4) 

(*4) 

[31] 

Write protect group enable

WP_GRP_ENABLE 

1 b 

Support 

[30:29] 2 

Reserved 

--- 

--- 

--- 

[28:26] 

Write speed factor 

R2W_FACTOR 

101 b 

32X 

[25:22] 

Max. write data block length

WRITE_BL_LEN 

9 h 

512 bytes 

[21] 

Partial block write allowed 

WRITE_BL_PARTIAL 

1 b 

Support 

[20:16] 5 

Reserved 

--- 

--- 

--- 

[15] 

File format group 

FILE_FORMAT_GRP 

0 b 

HD like FAT 

Summary of Contents for Secure Digital Card TS2GSD150

Page 1: ...25 85 C Insertion removal durability 10 000 cycles Fully compatible with SD card spec v1 1 Mechanical Write Protection Switch Support clock frequencies 0 50MHz Support different Bus width x1 x4 Suppor...

Page 2: ...T T TS S S2 2 2G G GS S SD D D1 1 15 5 50 0 0 2GB 150x Secure Digital Card Transcend Information Inc 2 Architecture...

Page 3: ...ta data can be transferred from the card to the host or vice versa Data is transferred via the data lines Figure 4 no response and no data operations Card addressing is implemented using a session add...

Page 4: ...data lines used for transferring the data Figure 6 Multiple Block write operation Command tokens have the following coding scheme Figure 7 Command token format Each command token is preceded by a sta...

Page 5: ...is transmitted first the LSB bit is the last When the wide bus option is used the data is transferred 4 bits at a time refer to Figure 10 Start and end bits as well as the CRC bits are transmitted for...

Page 6: ...t will respond with an error response which replaces the expected data block rather than by a time out as in the SD mode In addition to the command response every data block sent to the card during wr...

Page 7: ...e token and will wait for a data block to be sent from the host CRC suffix block length and start address restrictions are identical to the read operation see Figure 13 Figure 13 Write operation After...

Page 8: ...0000 b 7 1 65V 1 95V 0 b 14 8 2 0V 2 6V 000 0000 b 23 15 2 7V 3 6V 1 1111 1111 b 30 24 Reserved 000 0000 b 31 Card power status bit 1 OCR bit 31 is set to LOW if the card has not finished the power u...

Page 9: ...erved 119 112 8 Data read access time 1 TAAC 7F h 80 ms 111 104 8 Data read access time 2 NSAC FF h 25 5k clocks 103 96 8 Max bus clock freq TRAN_SPEED 32 h 25 MHz 95 84 12 Card command classes CCC 1F...

Page 10: ...4 This field is not a constant value The value will be changed by different flash memory 6 Extended CSD Register EXT_CSD The Extended CSD register defines the card properties and selected modes It is...

Page 11: ...total capacitance CL the CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST the bus capacitance CBUS itself and the capacitance CCARD of each card connected to this lin...

Page 12: ...ly voltage To meet the requirements of the JEDEC specification JESD8 1A the card input and output voltages shall be within the following specified ranges for any VDD of the allowed voltage range Param...

Page 13: ...min VIH and max VIL Clock frequency Data Transfer Mode fPP 0 25 MHz CL 100 pF 7 cards Clock frequency Identification Mode The low freq is required for MultiMediaCard compatibility fOD 0 400 KHz CL 25...

Page 14: ...cards Clock fall time 50 ns CL 250 pF 21 cards Inputs CMD DAT referenced to CLK Input set up time tISU 5 ns CL 25 pF 1 cards Input hold time tIH 5 ns CL 25 pF 1 cards Outputs CMD DAT referenced to CLK...

Page 15: ...Min Max Unit Remark Clock CLK All values are referred to min VIH and max VIL Clock frequency Data Transfer Mode fPP 0 50 MHz Clock low time tWL 7 ns Clock high time tWH 7 ns Clock rise time tTLH 3 ns...

Page 16: ...GS S SD D D1 1 15 5 50 0 0 2GB 150x Secure Digital Card Transcend Information Inc 16 Output Delay time during Data Transfer Mode tODLY 14 ns Output Hold time tOH 2 5 ns Total System capacitance for e...

Page 17: ...UV light exposure UV 254nm 15Ws cm according to ISO 7816 1 Visual inspection Shape and form No warp page no mold skin complete form no cavities surface smoothness 0 1 mm cm within contour no cracks no...

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