T
T
T
S
S
S
2
2
2
G
G
G
S
S
S
D
D
D
1
1
1
5
5
5
0
0
0
2GB 150x Secure Digital Card
Transcend Information Inc.
6
SPI bus
While the SD channel is based on command and data bit streams which are initiated by a start bit and terminated by
a stop bit, the SPI channel is byte oriented. Every command or data block is built of 8-bit bytes and is byte aligned to
the CS signal (i.e. the length is a multiple of 8 clock cycles).
Similar to the SD protocol, the SPI messages consist of command, response and data-block tokens All
communication between host and cards is controlled by the host (master). The host starts every bus transaction by
asserting the CS signal low.
The response behavior in the SPI mode differs from the SD mode in the following three aspects:
• The selected card always responds to the command.
• Two new (8 & 16 bit) response structure is used
• When the card encounters a data retrieval problem, it will respond with an error response (which replaces the
expected data block) rather than by a time-out as in the SD mode.
In addition to the command response, every data block sent to the card during write operations will be responded
with a special data response token.
• Data Read
Single and multiple block read commands are supported in SPI mode. However, in order to comply with the SPI
industry standard, only two (unidirectional) signal are used. Upon reception of a valid read command the card will
respond with a response token followed by a data token of the length defined in a previous SET_BLOCKLEN
(CMD16) command. A multiple block read operation is terminated, similar to the SD protocol, with the
STOP_TRANSMISSION command.
Figure 11: Read operation
A valid data block is suffixed with a 16 bit CRC generated by the standard CCITT polynomial X
16
+X
12
+X
5
+1.
In case of a data retrieval error, the card will not transmit any data. Instead, a special data error token will be sent to
the host Figure 12 shows a data read operation which terminated with an error token rather than a data block.
