T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
~
~
~
1
1
1
G
G
G
C
C
C
F
F
F
8
8
8
0
0
0
80X CompactFlash Card
Transcend Information Inc.
V1.1
40
Note: Because of the overlapped registers, PC Card modes access to the 1F1h, 171h or offset 1 are not defined for word
(-CE2 = 0 and -CE1 = 0) operations. These accesses are treated as accesses to the Word Data Register. The duplicated
registers at offsets 8, 9 and Dh have no restrictions on the operations that can be performed by the socket.
Table: Data Register Access
Notes: 1) -REG signal is mode dependent. Signal shall be 0 for I/O mode and 1 for Memory Mode.
5.5.2 Error Register (Address - 1F1h[171h]; Offset 1, 0Dh Read Only)
This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status
register. The bits are defined as follows:
Figure: Error Register
This register is also accessed in PC Card Modes on data bits D15-D8 during a read operation to offset 0 with -CE2 low
and -CE1 high.
Bit 7 (BBK)
: this bit is set when a Bad Block is detected.
Bit 6 (UNC)
: this bit is set when an Uncorrectable Error is encountered.
Bit 5
: this bit is 0.
Bit 4 (IDNF)
: the requested sector ID is in error or cannot be found.
Bit 3
: this bit is 0.
Bit 2 (Abort)
This bit is set if the command has been aborted because of a CompactFlash Storage Card status condition:
(Not Ready, Write Fault, etc.) or when an invalid command has been issued.
Bit 1
This bit is 0.
Bit 0 (AMNF)
This bit is set in case of a general error.
