T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
~
~
~
1
1
1
G
G
G
C
C
C
F
F
F
8
8
8
0
0
0
80X CompactFlash Card
Transcend Information Inc.
V1.1
27
3.12 True IDE Multiword DMA Mode Read/Write Timing Specification
The timing diagram for True IDE DMA mode of operation in this section is drawn using the conventions in the ATA-4
specification. Signals are shown with their asserted state as high regardless of whether the signal is actually negative or positive
true. Consequently, the -IORD, the -IOWR and the -IOCS16 signals are shown in the diagram inverted from their electrical states
on the bus.
Item
Mode 0
(ns)
Mode 1
(ns)
Mode 2
(ns)
Mode 3
(ns)
Mode 4
(ns)
Note
t
O
Cycle time (min)
480
150
120
100
80
1
t
D
-IORD / -IOWR asserted width (min)
215
80
70
65
55
1
t
E
-IORD data access (max)
150
60
50
50
45
t
F
-IORD data hold (min)
5
5
5
5
5
t
G
-IORD/-IOWR data setup (min)
100
30
20
15
10
t
H
-IOWR data hold (min)
20
15
10
5
5
t
I
DMACK to –IORD/-IOWR setup (min)
0
0
0
0
0
t
J
-IORD / -IOWR to -DMACK hold (min)
20
5
5
5
5
t
KR
-IORD negated width (min)
50
50
25
25
20
1
t
KW
-IOWR negated width (min)
215
50
25
25
20
1
t
LR
-IORD to DMARQ delay (max)
120
40
35
35
35
t
LW
-IOWR to DMARQ delay (max)
40
40
35
35
35
t
M
CS(1:0) valid to –IORD / -IOWR
50
30
25
10
5
t
N
CS(1:0) hold
15
10
10
10
10
t
Z
-DMACK
20
25
25
25
25
