User's Manual l TQMa335xL UM 0101 l © 2019, TQ-Systems GmbH
Page 26
3.3
TQMa335xL interface
3.3.1
Pin assignment
The multiple pin configurations of all AM335x-internal function units must be taken note of.
The pin assignment shown in Table 38 refers to the corresponding
BSP provided by TQ-Systems GmbH
The electrical and pin characteristics are to be taken from the AM335x (1), (3) and PMIC Data Sheet (6).
3.3.2
Pinout TQMa335xL
The TQMa335xL has a total of 209 pads. The following table shows the pad-out as top view through the TQMa335xL.
(NC: the pad does not exist.)
Table 38:
Pinout TQMa335xL, top view through TQMa335xL
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
17
NC
MCASP0
_FSX
MCASP0
_FSR
CLKOUT1 MMC0
_DAT0
MMC0
_CLK
USB0
_DM
USB0
_DP
USB0
_VBUS
RGMII1
_TD2
RGMII1
_TD0
RGMII1
_RD2
RGMII1
_RD0
USB1
_DM
USB1
_DP
USB1
_VBUS
NC
16 MCASP0
_AXR0
MCASP0
_AXR1
MCASP0
_ACLKR
DGND
MMC0
_DAT1
DGND
USB0
_CE
USB0
_ID
USB0_
DRVVBUS
RGMII1
_TD3
RGMII1
_TD1
RGMII1
_RD3
RGMII1
_RD1
DGND
USB1
_CE
USB1
_ID
USB1_
DRVVBUS
15 MCASP0
_AXR2
MCASP0
_AXR3
MCASP0
_ACLKX
TCLKIN
MMC0
_DAT2
MMC0
_CMD
DGND
MDC
MDIO
RGMII1
_TCLK
RGMII1
_TCTL
RGMII1
_RCLK SPI1_CS0
UART4
_RXD
UART4
_TXD
RGMII2
_RD1
RGMII2
_RD0
14 VDDSHV
VDD-
USB
DGND
DGND
MMC0
_DAT3
SPI0_
CS0
SPI0_
SCLK
SPI0_
D0_MISO
SPI0_
D1_MOSI
DGND
RGMII1
_RCTL
SPI1_
D1
SPI1_
D0
SPI1_
SCLK
RGMII2
_RTCL
RGMII2
_RD3
RGMII2
_RD2
13
PMIC_
PWRON
PMIC_
INT1
VDDS-
CORE
VDDS-
MPU
DGND
NC
DGND
NC
NC
NC
NC
NC
NC
RGMII2
_RCLK
RGMII2
_TCTL
RGMII2
_TD1
RGMII2
_TD0
12
EXTINT#
DGND
DGND
PMIC_
SLEEP
NC
NC
NC
NC
NC
NC
NC
NC
NC
DGND
RGMII2
_TCLK
RGMII2
_TD3
RGMII2
_TD2
11 VDD-PLL
DGND
DGND
DGND
NC
NC
NC
NC
NC
NC
NC
NC
NC
LCD_
DATA23
LCD_
DATA22
LCD_
DATA21
LCD_
DATA20
10
DGND
DGND
VDDS-
RTC
VDDS
NC
NC
NC
NC
NC
NC
NC
NC
NC
LCD_
DATA19
LCD_
DATA18
LCD_
DATA17
LCD_
DATA16
9
VCC
3V3IN
VCC
3V3IN
VBACKUP
_PMIC
VDDA-
ADC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LCD_
DATA15
LCD_
DATA14
LCD_
DATA13
LCD_
DATA12
8
VCC
3V3IN
VCC
3V3IN
DGND
DGND
NC
NC
NC
NC
NC
NC
NC
NC
NC
LCD_
DATA11
LCD_
DATA10
LCD_
DATA9
LCD_
DATA8
7
VCC
3V3IN
VCC
3V3IN
VDDS-
DDR
WARM
RST#
NC
NC
NC
NC
NC
NC
NC
NC
DGND
LCD_
DATA7
LCD_
DATA6
LCD_
DATA5
LCD_
DATA4
6
DGND
DGND
EXT_
WAKEUP DGND
NC
NC
NC
NC
NC
NC
NC
NC
NC
LCD_
DATA3
LCD_
DATA2
LCD_
DATA1
LCD_
DATA0
5
AIN6
AIN7
DGND
TCK
DGND
NC
NC
NC
NC
NC
NC
NC
DGND
LCD_
HSYNC
LCD_
M_CLK
LCD_AS_
BIAS_EN
LCD_
PCLK
4
AIN4
AIN5
TDI
TDO
EMU0
DDR_
A0
DDR_
DQS#0
DDR_
DQS0
DGND
DDR_
DQ15
MMC1_
DAT2
MMC1_
DAT5
DGND
LCD_
VSYNC
DGND
DGND
DGND
3
AIN2
AIN3
TMS
TRST#
EMU1
DDR_
CK#
DDR_
CK
DDR_
DQ7
DDR_
DQS1
DDR_
DQS#1
MMC1_
DAT1
MMC1_
DAT4
MMC1_
DATA7
MMC1_
CLK
MMC1_
CMD
TIMER7
TIMER6
2
AIN0
AIN1
DGND
PWRON
RST_IN#
PWRON
RST_OUT#
DGND
DGND
DGND
UART3
_TXD
UART3
_RXD
MMC1_
DAT0
MMC1_
DAT3
MMC1_
DATA6
DGND
DGND
TIMER5
TIMER4
1
NC
DGND
I2C0_
SCL
I2C0_
SDA
I2C1_
SDA
I2C1_
SCL
DCAN0
_TX
DCAN0
_RX
DCAN1
_TX
DCAN1
_RX
UART0
_TXD
UART0
_RXD
DGND
GPIO1
_28
GPIO1
_29
GPIO2
_0
NC