User's Manual l TQMLS10xxA UM 0105 l © 2022, TQ-Systems GmbH
Page 10
4.6
JTAG
The JTAG interface is routed to the connectors. Signals TMS, and TRST# have 10 kΩ Pull-Ups to 1.8 V on the TQMLS10xxA.
Figure 6:
Block diagram JTAG interface
Signal TRST_CPU# is connected with PORESET# by resistors. TRST# is pulled at the same time as PORESET#, but can also be pulled
Low using an external debugger, while PORESET# remains unchanged.
Figure 7:
Wiring of JTAG_TRST# and PORESET#
The CPLD is also in the JTAG chain of the CPU.
CPLD
CPU
Board
Controller
TRST#
TDI
TDO
TDI TDO
TDI TDO
TMS
TCK
TQMLS10xxA
connectors
Figure 8:
Wiring of JTAG chain with CPU and CPLD
The JTAG access to the CPU is activated by default.
The Board Controller can be used to switch to the JTAG port of the CPLD.
