T6K04
2001-03-13 6/30
Function of Each Block
●
Interface logic
The T6K04 can be operated with 80 series MPU.
Fig.
1
shows an example of interface.
Fig.
1
●
Input register
The register stores 8 bit data from MPU. D / I signal discriminate between command data and display data.
●
Output register
This register stores 8 bit data from the display RAM. When display data is read, the display data specified
by the address of Address Counter is set in this register. After that, the address is automatically incremented
or decremented. Therefore, when an address is set, the correct data does not appear at the first data read.
The data at a specified address appears at the second data read.
●
X
−
address counter
X
−
address counter is 64
−
Up / Down counter. It holds the row address for the display RAM. Then it is
selected by the command, writing to or reading the data of display RAM causes the X
−
address to
automatically increment or decrement.
●
Y (Page)
−
address counter
The Y (Page)
−
address counter is changed by word length of the display data. In case of 8 bits per word, it is
1
6
−
Up / Down counter. And in case of 6 bits per word, it is 22
−
Up / Down counter. It holds the column
address for the display RAM. This counter is selected by the command. Writing to or reading the display
RAM causes the Y
−
address to automatically increment or decrement.
●
Z
−
address counter
The Z
−
address counter is 64
−
Up counter that provide the display RAM data for the LCD drive circuit. The
data stored in Z
−
Address Register is send to Z
−
Address counter as Z start address.
For instance, when Z start address is
1
6, the counter increment like this:
1
6,
1
7,
1
8···, 62, 63, 0,
1
, 2···
1
4,
1
5,
1
6. Therefore, the display start line is
1
6
−
line of the display RAM.
●
Up / Down register
The
1
bit data stored in this register selects Up or Down mode of X and Y (Page)
−
address counter.
