Toshiba T6K04 Handbook Download Page 10 | Manualshive

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T6K04

2001-03-13 10/30

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Voltage divider resistors, contrast control circuit

The T6K04 has on

−

chip resistors to divide bias voltage with OP

−

Amp., and a contrast control circuit.

The voltage bias is changed by the value of R

1

and R

2

. Details of resisters to divide bias voltage and contrast

control circuit are shown in Fig. 7 as follows.

Fig. 7

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Summary of Contents for T6K04

Page 1: ...EE1 VEE2 Package TCP TOSHIBA is continually working to improve the quality and reliability of its products Nevertheless semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress It is the responsibility of the buyer when utilizing TOSHIBA products to comply with the standards of safety in making a safe design for the ...

Page 2: ...ecially true for devices in which the surface back or side of the chip is exposed When designing circuits make sure that devices are protected against incident light from external sources Exposure to light both during regular operation and during inspection must be taken into account The products described in this document are subject to the foreign exchange and foreign trade laws The information ...

Page 3: ...T6K04 2001 03 13 3 30 Pin Configuration Note Above drawing describes pin configuration of the LSI Chip it doesn t define the tape carrier package ...

Page 4: ...put row signal data Master mode M S H Output Slave mode M S L Input DB0 DB7 I O Data bus D I I Input for Data Instruction select signal D I H Indicates that the data of DB0 to DB7 is the display data D I L Indicates that the data of DB0 to DB7 is the control data WR I Input for write select signal WR H Selected read WR L Selected write CE I Input for chip enable signal At write Data of DB0 to DB7 ...

Page 5: ...cts LCD drive duty is shown in the table as follows DS1 DS2 Duty 0 0 1 32 duty 0 1 1 48 duty 1 0 1 56 duty 1 1 1 64 duty VIN Power supply for DC DC converter Normally connect to VSS C1A C1B Connect with capacitance for doubler VOUT1 DC DC converter output 2 level C2A C2B Connect with capacitance for tripler VOUT2 DC DC converter output 3 level C3A C3B Connect with capacitance for quadrupler VOUT3 ...

Page 6: ...y the command writing to or reading the data of display RAM causes the X address to automatically increment or decrement Y Page address counter The Y Page address counter is changed by word length of the display data In case of 8 bits per word it is 16 Up Down counter And in case of 6 bits per word it is 22 Up Down counter It holds the column address for the display RAM This counter is selected by...

Page 7: ...8 bits per word or 6 bits per word Word length change circuit This circuit is controlled by the word length register In case of 8 bits per word data is transferred by 8 bits In case of 6 bits per word the way of data transfer is show in Fig 2 as follows Fig 2 Oscillator The T6K04 has an on chip oscillator When using this oscillator connect an external resistor between OSC1 and OSC2 when using exte...

Page 8: ...n Fig 4 Fig 4 Row driver circuit Row driver circuit consists of 64 drive circuits One of the four LCD driving level is selected by the combination of M internal signal and the data from the sift register Details of row driver circuit are shown in Fig 5 Fig 5 DC DC converter The T6K04 has an on chip DC DC converter The DC DC converter generates 2 VIN 2 level 3 VIN 3 level and 4 VIN 4 level See Fig ...

Page 9: ...T6K04 2001 03 13 9 30 Doubler 2 mode Fig 6 1 Tripler 3 mode Fig 6 2 Quadrupler 4 mode Fig 6 3 When using external power supply input the voltage to VEE1 and VEE2 and Unconnect the capacitance ...

Page 10: ...circuit The T6K04 has on chip resistors to divide bias voltage with OP Amp and a contrast control circuit The voltage bias is changed by the value of R1 and R2 Details of resisters to divide bias voltage and contrast control circuit are shown in Fig 7 as follows Fig 7 ...

Page 11: ...t ability of operation amplifier is maximum on a short period from the rising edge of SEG signal and the ability is down on the other period Display RAM The display RAM consists of 64 row 128 column cells It is 8192 bits It is directly bit mapped to the LCD The relation of display RAM to LCD is shown in Fig 8 When selecting 8 bits per word mode the display RAM is arranged as 16 pages and each page...

Page 12: ...T6K04 2001 03 13 12 30 8 bits per word mode 6 bits per word mode Fig 9 ...

Page 13: ...UP 1 DOWN 0 CHE 0 0 0 0 0 1 1 Test Mode Select OPA1 0 0 0 0 0 1 0 1 0 1 0 1 0 Ability of Op Amp Control 1 OPA2 0 0 0 0 0 0 1 0 1 0 1 0 Ability of Op Amp Control 2 SYE 0 0 0 0 1 Y Address 0 21 Y Page Address Set SZE 0 0 0 1 Z Address 0 63 Z Address Set SXE 0 0 1 0 X Address 0 63 X Address Set SCE 0 0 1 1 CONTRAST CONTROL 0 63 Contrast Set STRD 0 1 B 8 6 D R OP 0 Y X U D Status Read DAWR 1 0 Write D...

Page 14: ...tting L level to RST makes word length 8 bits per word X Y Page counter Up Down mode select UDE D I WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 0 0 X Counter Down mode 04H 0 0 0 0 0 0 0 1 0 1 X Counter Up mode 05H 0 0 0 0 0 0 0 1 1 0 Y Counter Down mode 06H 0 0 0 0 0 0 0 1 1 1 Y Counter Up mode 07H This command selects the counter and UP DOWN mode For instance when selecting X counter UP mo...

Page 15: ...ord mode this command selects one of the 22 pages from the display RAM Note When inputting L level to RST Y address is set up as 0 page Z Address set SZE D I WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 A A A A A A Set Up Range 40H to 7FH ZAD0 to ZAD63 This command set a voluntary X address of the display RAM as the top row of LCD screen For instance when Z address is 16 the top row of LCD screen is...

Page 16: ...contrast of LCD The contrast of LCD are 64 steps and command C0H is the brightest or command FFH is the darkest OP Amp control 1 OPA1 D I WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 A A A Set Up Range 14H to 17H This command set the power supplying ability of operational amplifier This command selects one of four steps of ability 14H of this command corresponds to minimum ability and 17H corr...

Page 17: ...B0 0 0 1 0 0 0 0 1 0 A A Set Up Range 08H to 0BH This command enhances the power supplying ability of OP Amp in a shot period from the rising edge of CL signal This command selects one of four steps of ability Note When inputting L level to RST OP Amp is set up as t 0 See Fig 10 Fig 10 ...

Page 18: ...0 the T6K04 is operating state OP OP Amp When OP 1 OP Amp ON When OP 0 OP Amp OFF Y X Counter When Y X 1 Y counter is selected When Y X 0 X counter is selected U D UP DOWN When U D 1 X and Y counter are up mode When U D 0 X and Y counter are down mode Write read display data DAWR DARD D I WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 D D D D D D D D DAWR Display Data Write 1 1 D D D D D D D D DARD Displa...

Page 19: ...ead the X address is automatically decremented by one When the X counter is selected Y counter does not count up or down Fig 11 Fig 12 shows a sample operating procedure for the Y address counter in the 8 bits words length mode After Reset is executed Y Page address becomes Page 0 then select Y Page Up mode and 8 bits words length mode After data has been written to or read the Y Page address coun...

Page 20: ...ead Y Page address becomes Page 21 Data read When reading data there are some occasions that dummy data read is needed That is because when the data read command is written into the data corresponding to address counter is moved to the Output Resister and the contents of the output resister is transferred by the next data read command Therefore when reading data next to power on or next to address...

Page 21: ...l H The state of busy flag is output on data in response to the command STRD During the busy flag is H no instruction will be accepted except command STRD The busy state period T is shown as follows 2 fOSC T 4 fOSC sec fOSC Frequency of OSC1 Oscillation frequency By using the frequency select pins FS1 FS2 the T6K04 set the relation between oscillation frequency fOSC and frame frequency fM Next tab...

Page 22: ...mode Slave chip COM1 COM64 are available Timing signals and power voltage are supplied from Master Chip EXP L One chip mode Disable expansion mode COM1 COM64 are available Do not select Fig 13 1 and 2 illustrate the application example of Disable expansion mode and enable expansion mode In Enable Expansion Mode Two chips mode As shown in Fig 13 2 Fig 14 Master chip supplies LCD drive signals and p...

Page 23: ...T6K04 2001 03 13 23 30 2 Expansion mode Fig 13 2 Fig 14 ...

Page 24: ...D Note 1 0 3 7 0 V Supply Voltage 2 VLC1 2 3 4 5 VEE1 VEE2 VDD 18 0 VDD 0 3 V Input Voltage VINP Note 1 2 0 3 VDD 0 3 V Operating Temperature Topr 20 75 C Storage Temperature Tstg 55 125 C Note 1 Referred to VSS 0 V Note 2 Applied data bus terminals and Input terminals expect VEE1 VEE2 VLC1 VLC2 VLC3 VLC4 VLC5 ...

Page 25: ...OMD FS1 FS2 DS1 DS2 Pφ Operating Freq fOSC 20 500 kHz OSC1 External Clock Freq fex 20 500 kHz OSC1 External Clock Duty fduty 45 50 55 OSC1 External Clock Rise Fall Time tr tf 50 ns OSC1 Current Consumption 1 IDD1 Note 1 300 420 µA VDD Current Consumption 2 IDD2 Note 2 400 530 µA VDD Current Consumption 3 IDDSTB Note 3 1 1 µA VDD Output Voltage Tripler Mode VO2 2 Note 4 4 50 4 90 V VOUT2 Output Vol...

Page 26: ...DS2 Pφ Operating Freq fOSC 20 500 kHz OSC1 External Clock Freq fex 20 500 kHz OSC1 External Clock Duty fduty 45 50 55 OSC1 External Clock Rise Fall Time tr tf 50 ns OSC1 Current Consumption 1 IDD1 Note 1 510 640 µA VDD Current Consumption 2 IDD2 Note 2 620 830 µA VDD Current Consumption 3 IDDSTB Note 3 1 1 µA VDD Output Voltage Tripler Mode VO1 1 Note 4 4 25 4 50 V VOUT1 Output Voltage Quadruplexe...

Page 27: ...2 100 100 mV VLC1 VLC2 VLC3 VLC4 VLC5 Note 1 VDD 3 0 V VSS 0 V 1 9 bias 1 64 duty VEE1 2 9 5 V Contrast control Max Op Amp ON DC DC OFF LCD out pin No Load VLC1 pin VDD VDD VEE 1 9 Vopoff VLC2 pin VDD VDD VEE 2 9 Vopoff VLC3 pin VDD VDD VEE 7 9 Vopoff VLC4 pin VDD VDD VEE 8 9 Vopoff VLC5 pin VDD VDD VEE Vopoff Note 2 VDD 3 0 V VSS 0 V 1 9 bias 1 64 duty VEE1 2 9 5 V Contrast control Max Op Amp ON ...

Page 28: ...T6K04 2001 03 13 28 30 2 Tripler mode 3 Quadrupler mode ...

Page 29: ... Time tDS 280 ns Data Hold Time tDHW 20 ns Data Delay Time tDD Note 350 ns Data Hold Time tDHR Note 20 ns VSS 0 V VDD 5 0 V 10 VLC5 0 V Ta 25 C Item Symbol Min Max Unit Enable Cycle Time tcycE 500 ns Enable Pulse Width PWEL 220 ns Enable Rise Fall Time tEr tEf 20 ns Address Set up Time tAS 60 ns Address Hold Time tAH 0 ns Data Set up Time tDS 60 ns Data Hold Time tDHW 10 ns Data Delay Time tDD Not...

Page 30: ...T6K04 2001 03 13 30 30 Application 1 T6K04 One chip mode Oscillation frequency maximum LCD drive bias 1 9 Using DC DC Converter ...

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