TOPSCCC EX-92622A, User Manual

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EX-92622A User Manual 52
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DRAM Timing Selectable
Use this item to increase the timing of the memory. This is related to the cooling of memory.
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CAS Latency Time
You can select CAS latency time in HCLKs 2, 3, or Auto. The board designer
should set the values in this field, depending on the DRAM installed. Do not change the values in
this field unless you change specifications of the installed DRAM or the installed CPU.
„
DRAM RAS# to CAS# Delay
When DRAM is refreshed, both rows and columns are addressed separately.
This field lets you insert a timing delay between the
CAS and RAS strobe signals, used when DRAM is written to, read from, or refreshed.
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DRAM RAS# Precharge
The precharge time is the number of cycles it takes for the RAS to
accumulate its charge before DRAM refresh. If insufficient time is allowed, refresh may be
incomplete and the DRAM may fail to retain data.
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Precharge Delay <tRAS>
„ The precharge time is the number of cycles it takes for DRAM to accumulate its charge before
refresh.
„
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at
F0000h-FFFFFh, resulting in better system performance. However, if any program writes to this
memory area, a system error may result. The default value is
“Disabled”
.
„
Video BIOS Cacheable
This item allows you to change the Video BIOS location from ROM to
RAM. Video Shadow will increase the video speed.
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Memory Hole At 15M-16M
Enabling this feature reserves 15MB to 16MB memory address space