TMC LI6BM, User Manual, Page: 48 / 113

Chapter 6 BIOS and System Setup
44 LI6BM User’s Manual
SDRAM RAS Precharge Time
The precharge time is the number of cycles it takes for the RAS to
accumulate its charge before DRAM refresh. If insufficient time is
allowed, refresh may be incomplete and the DRAM may fail to retain
data. The default setting is
3 .
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. The default setting is
3 .
Bank DRAM Timing
These fields define the speed of the DRAM memory onboard. The
options are
Normal , Medium , Fast , Turbo , SDRAM 8ns and
SDRAM10ns . By default, these fields are set to SDRAM 10ns .
SDRAM Cycle Length
This field sets the SDRAM cycle length to either 2 or 3. The default
setting is
3 .
DRAM Clock Select
The DRAM clock can be set to Host CLK or the CPU clock itself and to
66MHz . By default, this field is set to Host CLK .
DRAM Data Integrity Mode
This field sets the integrity mode of the DRAM memory onboard. The
default setting is
Non-ECC .
Read Around Write
DRAM optimization feature: If a memory read is addressed to a location
whose latest write is being held in a buffer before being written to
memory, the read is satisfied through the buffer contents, and the read is
not sent to the DRAM.
Concurrent PCI/Host
This field enables or disables the concurrent PCI/Host. The default
setting is
Disabled .
System BIOS Cacheable
When enabled, access to the system BIOS ROM addressed at
F0000H-FFFFFH is cached, provided that the cache controller is
disabled.
Video BIOS Cacheable
When enabled, access to video BIOS addressed at C0000H to C7FFFH is
cached, provided that the cache controller is disabled.