42
For the locking version option, additional com
ponents D2, S13, PLE and SKE are fitted. This circuit
prevents outgoing calls being made.
43 In the circuits associated with IC 1, C 1, C6,
C11 to C14, D4 and D7 are not required for initial
units, but the positions are provided for possible
future developments. If IC 1 is a TMC1 604 device,
D1 and R3 are omitted.
44 Most of the line current flows down the base of
TR2 and through TR 1. TR2 is then saturated in the
on state. TR 1 provides current amplification during
speech periods as it is configured as a current source
in series with the loop. TR1 and TR2 are switched off
during impulses and line breaks. Capacitor C3
maintains the positive supply rail for IC 1 under such
circumstances. R 1 0 provides a small bias current
which is used to start up the circuit. XL 1 is a 560kHz
ceramic resonator providing a clock signal for the
internal logic of IC 1 .
45 The signal from the microphone is amplified by
about 24dB by the IC microphone amplifier which is
one of a special low noise design. This amplifier also
provides a d.c. level-shift function which is applied,
together with the amplified microphone signal to the
base of TR1.
46 The signal from the line is obtained via an
attenuator R8 and R5 and is fed into the earphone
amplifier via C 1 0 where it is summed with the
sidetone signal from the microphone amplifier to
provide sidetone cancellation. The earphone amplifier
output stage consists of a large enhancement
transistor with an active driven load to provide the
drive required by a 600 ohm earphone.
4 7 Both the microphone and earphone amplifiers
have a line displacement gain which is controlled by
the AGC control system. This circuit takes a voltage
from the d.c. control block which is similar to that
found on the base of TR 1 and compares it with a
voltage reference multiplier circuit.
48 When a pushbutton key is depressed, the circuit
changes into the dial mode of operation and the
oscillator is started. The microphone amplifier is
disabled and its d.c. level-shift function is taken over
by the dial mode d.c. regulator. The earphone
amplifier is ramped to a low current state by the anti
ear click .circuit which is a clock driven integrator. The
button depression is verified by an anti-bounce
circuit, and if accepted, the circuit will impulse out
the required number. During impulses, the base of
TR 1 is pulled down, thus switching off TR 1 and TR2
since the latter's base current is also removed. For
the duration of the impulse, the circuit relies on the
charge stored in C 1 to maintain operation (hence the
necessity to reduce the earphone amplifier power
consumption). The chip can store up to 18 digits in
its memory, whilst signalling at any given time.
8
49
During signalling, the circuit may be subject to
line breaks caused by the exchange and these should
not interfere with the signalling. It is therefore
necessary for the circuit to reorganise these and to
conserve the power stored in C2 until the power
returns. However, should the break last for more
than a given period, it must be interpreted as a hook
switch down action, and therefore return to speech
mode. The chip contains a line break detector which
compares Vdd with the voltage at the emitter of TR2
and should the latter be of a lower voltage, the circuit
will assume it is a break and .switch off TR 1 and TR2.
The break is timed by the logic which resets the
circuit to speech mode if the break lasts for more
than 1 80ms. Should the power return before a period
of 1 80ms, the circuit will continue to pulse out.
50 On very long lines, Vdd may not be high enough
to maintain the operation of the logic during impulses
and line breaks if the normal d.c. control function
were to be applied. For this reason, a minimum Vdd
regulation is included which prevents Vdd dropping
below a given value before impulsing commences.
51 Links C, D and E set the impulse speed and ratio
according to the following:
Speed
Break/Make Ratio
Fit Link
1 0 p.p.s.
2: 1
D
1 0 p.p.s.
1.55:1
c
20 p.p.s.
2: 1
E
52 At the end of the signalling mode of operation,
the microphone amplifier is switched on and the
earphone amplifier is ramped back to normal again,
once the sequence is complete, the oscillator is
switched off.
53 For the KT1 Series telephones, link B is omitted
and C4 is 470nf, whilst for the KT4 Series, R6 is
omitted and C4 becomes 220nf.
(Figure 4)
KT1 Basic MF (Multi-Frequency) Version
54 The PCB is connected to the line via the line
cord terminal pins as follows:
Pin 1 - via optional message waiting lamp
circuit
Pin 2
Pin 3
Pin 4
B wire
Bell input
Earth Loop Recall (return)
Pin 5 - A wire
Pin 6 - Not used
55 The A and B wires (nominally 24V, 48V or 60V
d.c. lines) are routed via link L and the polarity bridge
D4, D5, D7 and D8. The polarity bridge, including
surge suppressor, D6, a 1 30V Zener diode, also
provides transient protection.
351 3 300 05070
