HELIOS SERIES USER MANUAL
17
LVCMOS Clock Frequency
Model
Clock Frequency
Helios 380
6.4286 MHz
Helios 640
12.857 MHz
Note:
1.
It is recommended to sample DV data at the rising edge of clock.
2.
The high level is valid for Line_Valid, Frame_Valid.
3.
On a certain line, after the Line_Valid turns to be valid (logic ‘1’) and lasts for n clocks, the data
from column 1 to column n are valid.
7-1 Digital Video
7-1-1 LVCMOS
The signals of LVCMOS video consist of a clock signal (Clock), a line valid
signal (Line_Valid), a frame valid signal (Frame_Valid), and 14-bits data signals
(DV0~DV13). There are two kinds of data formats which are 14-bits and 10-bits.
When original data (RAW) or temperature data (TMP) is selected, the data has 14
bits which are DV[13:0], among them, DV0 is LSB and DV13 is MSB. When data
after image processing (DRC) is selected, the data has 10 bits which are DV[9:0],
among them, DV0 is LSB, DV9 is MSB.
LVCMOS digital video can be enabled or disabled through control command.
Original data (RAW), temperature data (TMP), or data after image processing
(DRC) can be selected as output source when the LVCOMS digital video is
enabled.
When the original data (RAW) and temperature data (TMP) are selected, function
of polarity selection, digital zoom, digital detail enhancement, digital filter and
imaging denoising, and temperature display are not supported.
When data after image processing (DRC) is selected, function of digital zoom
and temperature display are not supported.
7.
Digital Video
