HELIOS SERIES USER MANUAL
19
7-1-2-2 LVDS_F
LVDS_F digital video includes one clock signal (LVDS_CLK), one synchronizing
signal (LVDS_SYNC), and two data signals (LVDS_DATA1 and LVDS_DATA2). It
also has two kinds of data format which are 14-bits and 10-bits. When original
data (RAW) or temperature data (TMP) is selected, the data has 14 bits. When
data after image processing (DRC) is selected, the data has 10 bits.
Each pixel occupies 7 clocks in 14 bits format and the high 7 bits data [9..7] are
transferred on LVDS_DATA2 and the low 7 bits data [6..0] are transferred on
LVDS_DATA1. In 10-bits data format, the high 3 bits data [9..7] are transferred on
LVDS_DATA2, and write ‘0’ to the remaining high bits on LVDS_DATA2. The low 7
bits data [6..0] are transferred on LVDS_DATA1.
LVDS_SYNC is the frame synchronization bits, and “111XXXX” is the frame
synchronization flag, “11XX1XX” is the pixel valid flag, “11XX0XX” is the idle state
flag, these flags are all MSB ahead.
LVDS_F digital video can be enabled or disabled by control command. When
it is enabled, original data (RAW), temperature data (TMP), and data after
image processing (DRC, DRC_Gray, DRC_Color) can be selected. When the
original data (RAW) and temperature data (TMP) are selected, the functions
of polarity selection, digital zoom, digital detail enhancement, digital filter and
imaging denoising,and menu display are not supported. When data after image
processing (DRC) is selected, the function of digital zoom and temperature
display are not supported.
LVDS_F Clock Frequency
Model
LVDS_CLK
Helios 380
45.000 MHz
Helios 640
90.000 MHz
