3-7
Themis Computer
3—Hardware Overview
Baseboard
3.1.8
XR17D152 Dual UART (DUART)
The Exar XR17D152 is a monolithic dual PCI bus Universal Asynchronous
Receiver and Transmitter (UART) designed to for 32-bit PCI bus and high-band-
width communication systems requirements. A global interrupt source register pro-
vides a complete interrupt status indication for both channels to speed up interrupt
parsing.
Each UART is independently controlled and has its own 16C550-compatible 5th
generation register set, transmit and receive FIFOs of 64 bytes, fully programmable
transmit and receive FIFO trigger levels, transmit/receive FIFO level counters, auto-
matic hardware flow control with programmable hysteresis, automatic software
(Xon/Xoff) flow control, automatic half-duplex control output, wireless IrDA (Infra-
red Data Association) infrared encoder/decoder, 8 multi-purpose definable I/Os, and
a 16bit general-purpose timer-counter.
3.1.9
ICS950403 System Clock
The ICS950403 is a main system clock generator that uses the newest technology to
adjust output clocks by configuring the frequency setting, output divider ratios,
selecting the ideal spread percentage, the output skew, the output strength, and
enabling/disabling each individual output clock. M/N control can configure output
frequency with a resolution of up to 0.1-MHz increments.
The ICS950403 supports HyperTransport Technology through the AMD 8111 I/O
Hub and its real-time TOD clock, which is connected externally to a lithium battery.
3.1.10
Complex PLD (CPLD)
The CPLD (Complex Programmable Logic Device) implements byte-swapping
between the Tundra Universe-II PCI-to-VME bridge and the VME64 bus. There are
two main functions of this PLD: one is to implement miscellaneous registers and
manipulate the address map of the Flash devices; the other is to implement the reset
logic.
3.1.11
FPGA
The FPGA (Field-Programmable Gate Array) resides on the LPC (Low Pin Count)
bus and is the conduit to the GPIO, X-bus flash, status LEDs, configuration jumpers
and solder beads, and buffer control switch.
Summary of Contents for TA64
Page 3: ...iii Themis Computer TA64 Hardware Manual VersionRevisionHistory Version 1 0 May 2006...
Page 4: ...iv Themis Computer TA64 Hardware Manual...
Page 16: ...xvi Themis Computer TA64 Hardware Manual...
Page 38: ...TA64 Hardware Manual 1 14 Themis Computer...
Page 58: ...3 10 Themis Computer TA64 Hardware Manual...
Page 78: ...4 20 Themis Computer TA64 Hardware Manual...
Page 96: ...5 18 Themis Computer TA64 Hardware Manual...
Page 124: ...A 28 Themis Computer TA64 Hardware Manual...
Page 152: ...E 6 Themis Computer TA64 Hardware Manual...