Component Descriptions
Model P5000HX Series CPU User’s Manual
69
PCI local BUS IDE
The PIIX3 integrates a high performance interface from
PCI to IDE. This interface is capable of accelerated PIO
data transfers as well as acting as PCI bus master on
behalf of an IDE DMA slave device. The IDE data trans-
fers command strobes, DMA request and grant signals,
and IORDY signal interface directly to the PIIX3. Also, the
IDE data lines interface directly to the PIIX3 and are buff-
ered to provide part of the ISA address bus as well as the
X-Bus chip select signals. Only PCI masters have access to
the IDE port. ISA bus masters cannot access the IDE I/O
port addresses.
ISA Interface
The PIIX3 incorporates a fully ISA Bus compatible master
and slave interface. The PIIX3 directly drives five ISA
slots without external data buffers. The ISA interface also
provides byte swap logic, I/O recovery support, wait state
generation, and SYSCLK generation. ISA refresh cycles
are generated by the refresh controller inside the PIIX3.
The ISA interface supports the following types of cycles:
•
PCI master initiated I/O and memory cycles to
the ISA bus
•
DMA compatible cycles between main memory
and ISA I/O, and ISA I/O and ISA memory.
•
Enhanced DMA cycles between PCI memory
and ISA I/O
•
ISA refresh cycles initiated by the PIIX3 or an
external ISA master
•
ISA master-initiated memory cycles to PCI,
and ISA master-initiated I/O cycles to the
internal PIIX3 registers.
