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Texas Microsystems P5000HX Series, User Manual

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Texas Microsystems P5000HX Series User Manual Download Page 3

Model P5000HX Series CPU User’s Manual

3

Notice

This equipment has been tested and found to comply with the limits for a Class A
digital device pursuant to Part 15 of the FCC Rules. These limits are designed to
provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can
radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful
interference, in which case the user will be required to correct the interference at the
user’s own expense.

This device complies with Part 15 of the FCC Rules. Operation is subject to the
following two conditions: (1) This device may not cause harmful interference, and (2)
this device must accept any interference received, including interference that may
cause undesired operation.

Changes or modifications not expressly approved by Texas
Microsystems could void the product warranty and the user’s
authority to operate the equipment.

This product also meets requirements for compliance with EN55022, Class B ITE.

All tradenames referenced are the service mark, trademark or registered trademark of the respective manufacturer.

Summary of Contents for P5000HX Series

Page 1: ...User s Manual Model P5000HX Series CPU 22875A June 5 1996 Texas Microsystems All Rights Reserved Printed in USA ...

Page 2: ...determines to personally affect the performance and reliability or where the equipment has been subject to misuse neglect or accident The rights and remedies granted to Buyer under this paragraph constitute Buyer s sole and exclusive remedy against Texas Microsystems its officers agents and employees for negligence inexcusable delay breach of warranty express or implied or for any default whatsoev...

Page 3: ...residential area is likely to cause harmful interference in which case the user will be required to correct the interference at the user s own expense This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 This device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause un...

Page 4: ...2 Check Switch Settings 16 2 4 Step 3 Connect Peripherals to Headers 18 2 5 Step 4 Install the Board 26 2 6 Step 5 Attach Peripherals to Connectors 28 2 7 Step 6 Power up the System 30 2 8 Step 7 Run the Setup Utility 32 CHAPTER 3 P5000HX Service and Support 47 3 1 Installing Memory 48 3 2 General Maintenance 50 3 3 Customer Support 52 CHAPTER 4 Technical Data 55 4 1 Specifications 56 4 2 Connecto...

Page 5: ...as Micro s P5000HX Series CPU This chapter introduces the primary features of the P5000HX and discusses the PCI backplane and PICMG If you wish to configure and install your P5000HX quickly and you are familiar with P5000HX features and PCI con cepts go directly to Chapter 2 then read this chapter at your convenience 1 ...

Page 6: ...DE and features 512 KByte flash memory and a CELP socket for optional high speed pipelined burst SRAM modules up to 512 KBytes Additional features include Support for up to 256 MByte scaleable FPM DRAM chip set allows ECC using standard SIMMs One RS 232 serial port one programmable RS 232 422 485 serial port a multi function enhanced IEEE 1284 parallel port a floppy disk controller an EIDE hard di...

Page 7: ...P5000HX Features Model P5000HX Series CPU User s Manual 7 FIGURE 1 P5000HX components ...

Page 8: ...architectures Moving peripheral functions with high bandwidth requirements closer to the system s processor bus can eliminate this bottleneck Substantial performance gains are seen with graphical user interfaces GUI s and other high bandwidth func tions i e full motion video SCSI LANs etc when a local bus design is used The PCI Bridge The processor cache memory subsystem in a PCI system is connect...

Page 9: ...A PCI Discussion Model P5000HX Series CPU User s Manual 9 FIGURE 2 A sample PCI backplane Texas Micro s 18 slot version ...

Page 10: ...PU 10 Model P5000HX Series CPU User s Manual This chapter covered P5000HX features basic P5000HX components the PCI Local Bus and Bridge PICMG Next The next chapter outlines the seven basic steps for P5000HX configuration and installation ...

Page 11: ...precautions for handling the P5000HX then outlines the seven basic steps for con figuring and installing the P5000HX Series CPU 1 Check jumper settings 2 Check switch settings 3 Connect peripherals to headers 4 Install the board 5 Attach peripherals to connectors 6 Power up the system and 7 Run the Setup Utility 2 ...

Page 12: ...afety considerations It is important to protect yourself and your equipment before you perform any of the following procedures Never touch the P5000HX while it is installed in the chas sis and power is ON You should check the P5000HX configuration before you install the board However if the P5000HX is already installed in your system remove power by turning all power switches OFF and disconnecting...

Page 13: ...Handling the P5000HX Model P5000HX Series CPU User s Manual 13 FIGURE 3 Handling the P5000HX ...

Page 14: ...JP4 JP5 and JP7 and two 2 two pin jumper blocks JP6 and JP8 Settings Settings for these jumper block are provided in the following tables JP2 JP3 JP5 Pin 2 jumpered to Pin 3 RS232 configuration default Pin 1 jumpered to Pin 2 RS422 485 configuration JP4 Pin 1 jumpered to Pin 2 Watchdog timer reset active enabled Pin 2 jumpered to Pin 3 Watchdog timer reset inactive default JP7 Pin 1 jumpered to Pi...

Page 15: ...ese jumper settings The P5000HX is very sensitive to static discharge and can be damaged if precautions are not taken See Section 2 1 on page 12 for more information JP6 jumper installed JP8 jumper installed Bus Core Frequency Ratio Bus Processor Speed Yes Yes 2 5 66 166 Yes No 1 3 66 200 No Yes 1 2 66 133 default No No 2 3 66 100 Bus Processor Speed Table ...

Page 16: ...provided below Switch Setting Result SW1 1 Open Monochrome monitor position Closed default Color monitor position SW1 2 Open default Flash memory is enabled auxiliary ROM is disabled Closed Auxiliary ROM is enabled Flash memory is disabled SW1 3 Open default Normal operation of the CMOS RAM Closed Used is special cases when the CMOS RAM becomes corrupted When this switch is CLOSED the factory defa...

Page 17: ...ngs Model P5000HX Series CPU User s Manual 17 FIGURE 5 Switch block location Note The P5000HX is very sensitive to static discharge and can be damaged if precautions are not taken See Section 2 1 on page 12 for more information ...

Page 18: ...s surface as opposed to connectors which are located on the I O bracket and are discussed in Section 2 6 on page 28 The P5000HX features the following headers for peripheral connection a PCI Bus to Fast and Wide SCSI controller an EIDE drive header an IDE SCSI drive LED header a floppy drive header a serial port header Serial Port 2 an AT style keyboard header and a PS 2 mouse header Descriptions ...

Page 19: ...eaders Model P5000HX Series CPU User s Manual 19 FIGURE 6 P5000HX header locations Note The P5000HX is very sensitive to static discharge and can be damaged if precautions are not taken See Section 2 1 on page 12 for more information ...

Page 20: ...than two 2 terminators can exist in a chain of SCSI devices one at each end of the physical chain If more than two SCSI devices are connected in a SCSI daisy chain the termination must be removed from the middle device s in the control cable EIDE Drive Header Two 2 Integrated Device Electronics EIDE backwards com patible with IDE hard disk drives can be attached to the P5000HX board via this heade...

Page 21: ...Step 3 Connect Peripherals to Headers Model P5000HX Series CPU User s Manual 21 FIGURE 7 SCSI EIDE and LED headers ...

Page 22: ...to connect serial devices a serial mouse serial printers etc to the P5000HX via appropriate serial cables Serial ports are also known as UART Universal Asyn chronous Receiver Transmitter ports Note The P5000HX uses 16550 UART s UART 2 the second serial port is a 10 pin header located on the card s front surface Be sure to use the proper cable when connecting a serial device to the P5000HX If con n...

Page 23: ...Step 3 Connect Peripherals to Headers Model P5000HX Series CPU User s Manual 23 FIGURE 8 Floppy drive and Serial Port 2 headers ...

Page 24: ...tor cable are numbered in reverse order when compared to the pinout of the P5000HX keyboard cable header For example Position 8 of the connector cable corresponds with Pin 1 of the header Posi tion 7 of the cable corresponds with Pin 2 of the header etc PS 2 Mouse Header A 10 pin 2x5 header allows connection with a cable adapter to a PS 2 mouse connector Next After you ve connected all desired per...

Page 25: ...Step 3 Connect Peripherals to Headers Model P5000HX Series CPU User s Manual 25 FIGURE 9 Keyboard and PS 2 Mouse headers ...

Page 26: ...lace 3 For PCI operation otherwise skip to step 4 Locate the platform or CPU slot If the CPU is installed in another slot it will be unable to communicate with any third party PCI adapter cards 4 Remove the I O bracket spacer from the rear of the chassis if required This spacer occupies the area where the card s I O bracket is accessed through the back of the chassis 5 Ensure that you ve connected...

Page 27: ...o install the P5000HX into a passive backplane not manufactured by Texas Micro follow the instructions provided by the backplane manufacturer If the P5000HX is installed in a non Texas Micro chassis a custom cable might be needed to adapt the keyboard connector to the wiring in the non Texas Micro chassis Texas Micro is unable to create such a cable ...

Page 28: ...nnect serial devices a serial mouse serial printers etc to the P5000HX via appropriate serial cables Serial ports are also known as UART Universal Asynchronous Receiver Transmitter ports Note The P5000HX uses 16550 UART s SERIAL 1 is a 9 pin connector located on the edge of the card on the I O bracket This means that you can access SERIAL 1 through the back of the chassis after the P5000HX is inst...

Page 29: ...Step 5 Attach Peripherals to Connectors Model P5000HX Series CPU User s Manual 29 FIGURE 10 Serial Port 1 and Parallel Port ...

Page 30: ...ower to your system If the P5000HX has been properly installed a power up ban ner will be displayed and a power up memory test will run Accessing the Setup Utility If desired you can now access the P5000HX Setup Utility The Setup Utility can be accessed by pressing F2 when prompted by the BIOS during the power up operation Next Turn to Section 2 8 on page 32 for instructions on using the P5000HX S...

Page 31: ... 1996 Weekday Monday Drive A 3 1 2 Inch 2 88 MB Drive B Not Installed Hard Disk 1 Type 40 is 514 MB Hard Disk 2 Not Installed Keyboard Typematic Delay 250 msec Keyboard Typematic Rate 30 char sec Base Memory 640K Extended Memory 007168K Floating Point Unit Operational Boot Drive Sequence Drive A then C 101 Keyboard NumLock Disabled Boot Option Diagnostic Boot Time and Date Floppy Disks Fixed Disks...

Page 32: ...ility is a special set of functions used to set the computer time date and configuration data Access As described on page 30 the Setup Utility can be accessed by pressing F2 when prompted by the BIOS during the power up operation Main Menu The Setup Utility begins by displaying the Main Menu screen pictured in Figure 12 Next Turn to page 34 for information on the Main Menu ...

Page 33: ... 88 MB Drive B Not Installed Hard Disk 1 Type 40 is 514 MB Hard Disk 2 Not Installed Keyboard Typematic Delay 250 msec Keyboard Typematic Rate 30 char sec Base Memory 640K Extended Memory 007168K Floating Point Unit Operational Boot Drive Sequence Drive A then C 101 Keyboard NumLock Disabled Boot Option Quiet Boot Time and Date Floppy Disks Fixed Disks Keyboard Shadow RAM Boot Options Password Edi...

Page 34: ...our system requirements Use these keys Summary The summary information area displays current system set tings information and is located to the right of the Options Menu F5 key If you are using an external monochrome VGA monitor and are experiencing trouble seeing the cursor when the Main Menu is displayed press the F5 key The Main Menu attributes will be switched from color to black and white mak...

Page 35: ...RAM Boot Options Password Edit Advanced Options PCI Options Time 10 18 28 Date July 1 1996 Weekday Monday Drive A 3 1 2 Inch 2 88 MB Drive B Not Installed Hard Disk 1 Type 40 is 514 MB Hard Disk 2 Not Installed Keyboard Typematic Delay 250 msec Keyboard Typematic Rate 30 char sec Base Memory 640K Extended Memory 007168K Floating Point Unit Operational Boot Drive Sequence Drive A then C 101 Keyboar...

Page 36: ... Compatible option should be enabled when you are running DOS based operating systems This option enables BIOS translation for drives greater than 528 MB Keyboard These three menus allow you to set these external keyboard Typematic options sound if enabled the system speaker will click as you press keys on the external keyboard delay the period that elapses between the time a key is held down unti...

Page 37: ...Translate Mode LBA I O Transfer Size 16 Bit Transfer Mode Standard Block Transfer Sectors 1 Set Hard Disk 1 Type Not Installed 5 1 4 Inch 360 KB 5 1 4 Inch 1 2 MB 3 1 2 Inch 720 KB 3 1 2 Inch 1 44 MB 3 1 2 Inch 2 88 MB Select Drive Type Disabled Enabled Keyboard Typematic Sound 250 MSec 500 MSec 750 MSec 1000 MSec Keyboard Typematic Delay 30 Chars sec 20 Chars sec 2 5 Chars sec Keyboard Typematic ...

Page 38: ...rting address length and status for each option ROM Boot Options The first menu allows you to set the NumLock key status at boot If a 101 key keyboard is attached this option directs the BIOS to enable disable the NumLock key before booting The second menu allows you to set the boot drive sequence The third allows for a quiet boot a banner will be displayed rather than power up diagnostics Passwor...

Page 39: ...ime and Date Floppy Disks Fixed Disks Keyboard Shadow RAM Boot Options Password Edit Advanced Options PCI Options Address C000 0 Length 32K Status SHADOW Shadow Select SHADOW SHADOW SHADOW SHADOW DC00 D800 D400 D000 CC00 C800 C400 C000 Shadow RAM Definitions 101 Key Keyboard NumLock at Boot Password Edit Set Boot Drive Sequence Password Options E000 EFFF F000 FFFF CPU BIOS Diagnostic Boot Quiet Bo...

Page 40: ...ws you to enable or disable the external L2 write back cache Advanced Chipset This menu allows you to configure four options DRAM Speed set this option to match the speed of installed SIMMs Caution should be used when changing defaults incorrect settings can damage the system DMA Alias the DMA Alias feature is an I O range switch for the chip that is responsible for bridging the PCI to ISA bus Ena...

Page 41: ...s Parallel Ports Memory Cache Advanced Chipset I O Recovery Bus Speed Miscellaneous PCI Options Basic Options AT Compatible PS 2 Compatible Parallel Port Mode Disabled 0378h IRQ7 0278h IRQ7 0378h IRQ5 0278h IRQ5 Select Parallel Port Address Disabled Enabled External Cache 60 ns 70 ns DRAM Speed Disabled Parity ECC Parity ECC Config Disabled Enabled DMA Alias Disabled 512 640k 15 16 MB Memory Gap B...

Page 42: ...overy time in essence providing additional wait states ISA Bus Speed This menu allows you to configure the P5000HX to match your system s ISA Bus Speed Miscellaneous This menu allows you to configure three options You can enable disable the on board speaker You can enable disable the on board PS 2 mouse and You can set the watchdog timer delay which will be in effect if jumper JP4 is configured fo...

Page 43: ...to ISA I O slaves Minimum is 3 5 SYSCLKs Total Recovery 3 5 SYSCLK 4 5 SYSCLK 5 5 SYSCLK 6 5 SYSCLK 7 5 SYSCLK 8 5 SYSCLK 9 5 SYSCLK 10 5 SYSCLK 11 5 SYSCLK 8 Bit I O Recovery Time Provides additional delays between back to back PCI cycles to ISA I O slaves Minimum is 3 5 SYSCLKs Total Recovery 3 5 SYSCLK 4 5 SYSCLK 5 5 SYSCLK 6 5 SYSCLK 7 5 SYSCLK 16 Bit I O Recovery Time Disabled Enabled Speaker...

Page 44: ...nd in the system Do not route the PCI inter rupt to an ISA interrupt that is already being used by an ISA device INTA INTB INTC or INTD the PCI bus interrupts may share a common ISA interrupt If a PCI interrupt is not used it will not be routed to the ISA bus nor will you have the option of routing the interrupt You can use the Auto option to automatically route the PCI devices but only if no ISA ...

Page 45: ...IRQs already in use by ISA devices Use Auto only if no legacy cards are installed Available IRQs Disabled Auto IRQ51 IRQ9 IRQ10 IRQ11 IRQ122 IRQ143 IRQ15 PCI INTA Bus Device 00 00 Function 00 VenID DevID 0x8086 0x0483 Device Type Original PCI Non VGA IRQ Binding No IRQ PCI Devices Disabled Enabled Onboard PCI SCSI 1 Only if IRQ 5 is not enabled in the Parallel Port Menu 2 Only if the PS 2 mouse is...

Page 46: ...P5000HX Series CPU User s Manual This chapter covered P5000HX handling jumper configuration switch setting peripheral connection power up the Setup Utility Next The next chapter provides procedures for upgrading and main taining the P5000HX ...

Page 47: ...ovides information on Installing extra memory Maintaining the P5000HX Calling the Texas Microsystems Technical Support line Returning products for service Accessing the Texas Microsystems Bulletin Board System BBS and InfoLine fax service and Accessing the Texas Micro Home Page on the Internet 3 ...

Page 48: ...talled in SIMM sockets 1 2 3 or 4 as shown in Figure 19 Sockets 1 and 2 comprise Bank 0 Sockets 3 and 4 comprise Bank 1 Banks must be completely filled to be operable i e if a 1 MByte SIMM is installed in Socket 1 another 1 MByte SIMM must be installed in Socket 2 etc The table on the following page summarizes the supported configurations Note The P5000HX board s gold sockets require gold SIMM s T...

Page 49: ...ty 32 MB 4M x 36 16 MB 1M x 36 8 MB 40 MB 4M x 36 16 MB 2M x 36 8 MB 48 MB 4M x 36 16 MB 4M x 36 16 MB 64 MB 8M x 36 32 MB Empty 64 MB 8M x 36 32 MB 1M x 36 4 MB 72 MB 8M x 36 32 MB 2M x 36 8 MB 80 MB 8M x 36 32 MB 4M x 36 16 MB 96 MB 8M x 36 32 MB 8M x 36 32 MB 128 MB 16M x 36 64 MB Empty 128 MB 16M x 36 64 MB 1M x 36 4 MB 136 MB 16M x 36 64 MB 2M x 36 8 MB 144 MB 16M x 36 64 MB 4M x 36 16 MB 160...

Page 50: ...tact P5000HX com ponents damage to sensitive components may occur Inspect all cables and connectors to verify that they are securely fastened to their connecting components Replace worn or stressed cables and connectors All peripheral equipment used with the P5000HX should be properly maintained Malfunctioning equipment should be immedi ately replaced to prevent damage to the P5000HX CPU Lithium b...

Page 51: ...ry location WARNING Due to risk of fire or explosion do not recharge force open or heat the P5000HX battery or dispose of the battery in fire WARNING Improper replacement of the battery may cause damage to the P5000HX and void the warranty acquired with the purchase of the P5000HX Card ...

Page 52: ... service the factory must be contacted and a Return Goods Autho rization RGA number must be obtained from a Technical Support Representative BBS Texas Microsystems provides a BBS service that enables customers with modem communications packages to download several types of software new BIOS versions software drivers etc for their Texas Microsystems prod ucts The BBS is in operation 24 hours a day ...

Page 53: ...ization RGA number is assigned place it along with the product serial number on any packing materials and correspon dence The factory will be unable to accept delivery without these numbers Accessing the BBS available anytime Step Action 1 Dial 713 541 8250 add any appropriate long distance international access dialing codes 2 Set your communication program to use ANSI sometimes called ANSI BBS as...

Page 54: ...ce and Support 54 Model P5000HX Series CPU User s Manual This chapter covered DRAM installation P5000HX maintenance and Customer support Next Specifications and technical information are provided for your reference ...

Page 55: ...Model P5000HX Series CPU User s Manual 55 CHAPTER 1 Technical Data This chapter provides specifications connector pinouts and component level data for the P5000HX Series CPU Board 4 ...

Page 56: ...ata 56 Model P5000HX Series CPU User s Manual 4 1 Specifications Overview Specifications for the P5000HX board are provided in the table on the facing page Note Specifications are subject to change without notice ...

Page 57: ...perating Non Operating 5 to 95 40 C non condensing 0 to 95 40 C non condensing Shock Operating Non Operating 1 25G 10ms 10 0G 11 ms in appropriate chassis 30 0G 10ms 40 0G 11 ms in appropriate chassis Vibration Operating Non Operation 25G 5Hz to 100Hz 1 5G over 5Hz to 100Hz in appropriate chassis 5G 5Hz to 100Hz Altitude Operating Non Operating 15 000 feet 4572 meters 50 000 feet 15 240 meters ...

Page 58: ...ext Turn to page 60 for additional pinouts Pin Signal Name 1 DCD Data Carrier Detect 2 RXD Receive Data 3 TXD Transmit Data 4 DTR Data Terminal Ready 5 GND Signal Ground 6 DSR Data Set Ready 7 RTS Request to Send 8 CTS Clear to Send 9 RI Ring Indicator Pin Signal Name Pin Signal Name 1 DCD Data Carrier Detect 2 DSR Data Set Ready 3 RX Receive Data 4 RTS Request to Send 5 TX Transmit Data 6 CTS Cle...

Page 59: ...nected 10 5V RS 422 485 Pinout Serial Port 2 UART 2 Note The Pin numbers above are appropriate for con necting two Texas Micro CPU cards through the 10 pin headers only Pin No Description 1 Z Output TX 3 Y Output TX 2 B Receive RX 6 A Receive RX Pin No Description 2 B Receive RX 6 A Receive RX 1 Z Output TX 3 Y Output TX Machine A Machine B To connect two RS 485 devices use a shielded twisted pair...

Page 60: ...or 7 Data Bit 5 16 Init Printer 8 Data Bit 6 17 Select Input 9 Data Bit 7 18 25 Ground Pin Signal Name Pin Signal Name 1 Reset output 2 Ground 3 Data 7 input output 4 Data 8 input output 5 Data 6 input output 6 Data 9 input output 7 Data 5 input output 8 Data 10 input output 9 Data 4 input output 10 Data 11 input output 11 Data 3 input output 12 Data 12 input output 13 Data 2 input output 14 Data ...

Page 61: ...page 62 for more pinouts 23 I O Write output 24 Ground 25 I O Read output 26 Ground 27 No connection 28 ALE output 29 No connection 30 Ground 31 IRQ 14 input 32 I O CS16 output 33 ADDR1 output 34 No connection 35 ADDR0 output 36 ADDR2 output 37 CS0 output 38 CS1 output 39 Activity light output 40 Ground Pin Signal Name Pin Signal Name ...

Page 62: ...output active low 15 Ground 16 Motor enable Drive B output active low 17 Ground 18 Head step direction output active low 19 Ground 20 Head step pulse output active low 21 Ground 22 Write data output active low 23 Ground 24 Write gate output active low 25 Ground 26 Track 0 detect input active low 27 Ground 28 Write protect sense input active low 29 Ground 30 Read data input active high 31 Ground 32...

Page 63: ... 63 AT style Keyboard FIGURE 24 Pin orientation Floppy PS 2 Mouse Keyboard Next Turn to page 64 for the SCSI connector pinout Pin Signal Name Pin Signal Name 1 Reset 5 Keyboard Data 2 Ground 6 Keyboard Lock 3 No connection 7 5V Out 4 Keyboard Clock 8 Speaker ...

Page 64: ...4 I O 4 Ground 38 DB15 I O 5 Ground 39 DBPH I O 6 Ground 40 DB0 I O 7 Ground 41 DB1 I O 8 Ground 42 DB2 I O 9 Ground 43 DB3 I O 10 Ground 44 DB4 I O 11 Ground 45 DB5 I O 12 Ground 46 DB6 I O 13 Ground 47 DB7 I O 14 Ground 48 DBPL I O 15 Ground 49 Ground 16 Ground 50 Ground 17 TRMPWR 51 TRMPWR 18 TRMPWR 52 TRMPWR 19 Reserved 53 Reserved 20 Ground 54 Ground 21 Ground 55 ATN Output 22 Ground 56 Groun...

Page 65: ...rientation SCSI Connector 25 Ground 59 RST I O 26 Ground 60 MSG Input 27 Ground 61 SEL I O 28 Ground 62 CD Input 29 Ground 63 REQ Input 30 Ground 64 I O Input 31 Ground 65 DB8 I O 32 Ground 66 DB9 I O 33 Ground 67 DB10 I O 34 Ground 68 DB11 I O Pin Signal Name Pin Signal Name ...

Page 66: ...nal cache is complemented with a 256 512 KB write back second level cache imple mented with optional pipelined burst SRAM modules Tag and control logic is contained in the 82430HX TXC core chip External tag 16k x 4 has been added for cacheability detection of up to 512KB cache Triton II Xcellerated Controller TXC The Triton II Xcellerated Controller TXC is a single chip host to PCI bridge providin...

Page 67: ...ulti function PCI device implementing a PCI to ISA bridge function and a PCI IDE function In addition the PIIX3 implements a host hub function The PIIX3 integrates many common I O functions found in ISA based PC sys tems a seven Channel DMA controller two 82C59 inter rupt controllers an 8254 timer counter and power management support The DMA supports compatible and Type F transfers The chip select...

Page 68: ...SA compatible registers except for the DMA register I O space which is subtract decoded The PIIX3 also provides positive decoding for BIOS and X Bus and system event decoding for SMM sup port The PIIX3 positively decodes PCI bus accesses to reg isters located on the IDE device when this is enabled DMA Controller The DMA controller incorporates the functionality of two 82C37 DMA controllers with se...

Page 69: ... cannot access the IDE I O port addresses ISA Interface The PIIX3 incorporates a fully ISA Bus compatible master and slave interface The PIIX3 directly drives five ISA slots without external data buffers The ISA interface also provides byte swap logic I O recovery support wait state generation and SYSCLK generation ISA refresh cycles are generated by the refresh controller inside the PIIX3 The ISA...

Page 70: ...standard PCI cycle terminations as described in the PCI local configuration Timer Block The timer block contains three counters that are equiva lent in function to those found in one 82C54 programma ble interval timer These three counters are combined to provide the System Timer function Refresh Request and speaker tone Utility Bus X Bus Logic Chip selects for Flash BIOS real time clock keyboard m...

Page 71: ...ect NOT USED Supports DMA with type F transfers Five programmable ISA interrupt lines Serial ports can be configured via setup pro gram as either IRQ3 or IRQ4 Keyboard PS 2 Mouse Interface An Intel S82C42PC surface mount microcontroller con tains the Phoenix Technologies compatible keyboard mouse controller code An 8 pin header allows connection with a cable adapter to an AT style keyboard connect...

Page 72: ... an I O coproces sor to offload the host CPU Active termination is provided through two monolithic ICs containing the voltage regula tor voltage reference and resistors circuits The AIC 7870 features the following True 32 bit PCI bus master DMA implementa tion Maximizes data transfer on PCI local bus at 133 Mbytes sec data bursts Low SCSI command overhead of 50 ms greatly improves command executio...

Page 73: ...stored in an auxiliary boot ROM and in a Flash EEPROM for upgradability using a floppy disk based pro gram In addition to the BIOS the Flash EEPROM also contains the Setup Utility Power On Self Test POST update recovery code and the PCI auto configuration utility Flash Implementation The FLASH component is organized as 512K x 8 512 KB The Flash device is divided into four areas as described in the...

Page 74: ...Notes 74 Model P5000HX Series CPU User s Manual NOTES ...

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