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Model P5000HX Series CPU User’s Manual
Component Descriptions (cont.)
Overview
The following section describes each of the major functions
on the 82430HX-PIIX3 including the memory and I/O
address map, DMA controller, interrupt controller, timer/
counter, and power management:.
The PCI, ISA, X-bus
and IDE interfaces
The PIIX3 interfaces to two system buses-- PCI and ISA
buses. The PIIX3 provides some positive decode for certain
I/O and memory space accesses on these buses as
described in the next sections.
I/O Access
The PIIX3 positively decodes accesses to the PCI configu-
ration registers, power management registers, APIC regis-
ters, and bus master IDE interface registers. Also, the
PIIX3 positively decodes the ISA compatible registers,
except for the DMA register I/O space, which is subtract
decoded. The PIIX3 also provides positive decoding for
BIOS and X-Bus and system event decoding for SMM sup-
port. The PIIX3 positively decodes PCI bus accesses to reg-
isters located on the IDE device when this is enabled.
DMA Controller
The DMA controller incorporates the functionality of two
82C37 DMA controllers with seven independently pro-
grammable channels. Each channel can be programmed
for 8 or 16-bit DMA device size and ISA-compatible or fast
DMA type “A,” type “B,” or type “F” timings. The PIIX3
provides 24 bit address in compliance with ISA specifica-
tions. Type F” DMA is selected via the MBDMA[1:0] regis-
ters and permits up to two channels to be programmed for
type “F” transfers at the same time.
Type F cycles occur back to back at a minimum repetition
rate of three SYSCLKs.
Verify transfers are not supported with type F DMA.
